Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368586 ◽

2000 ◽

Cited By ~ 4

Author(s):

Takahiro Deguchi ◽

Tetsushi Koide ◽

Shin'ichi Wakabayashi

Keyword(s):

Global Routing ◽

Buffer Insertion ◽

Wire Sizing

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Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835078 ◽

2002 ◽

Cited By ~ 2

Author(s):

T. Deguchi ◽

T. Koide ◽

S. Wakabayashi

Keyword(s):

Global Routing ◽

Buffer Insertion ◽

Wire Sizing

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A performance-driven global routing algorithm with wire-sizing and buffer-insertion

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242) ◽

10.1109/apccas.1998.743673 ◽

2002 ◽

Author(s):

T. Deguchi ◽

T. Koide ◽

S. Wakabayashi

Keyword(s):

Routing Algorithm ◽

Global Routing ◽

Buffer Insertion ◽

Wire Sizing ◽

A Performance

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.766728 ◽

1999 ◽

Vol 18 (6) ◽

pp. 787-798 ◽

Cited By ~ 30

Author(s):

C.C.N. Chu ◽

D.F. Wong

Keyword(s):

Quadratic Programming ◽

Programming Approach ◽

Buffer Insertion ◽

Wire Sizing

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Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2006.884869 ◽

2007 ◽

Vol 26 (5) ◽

pp. 845-857 ◽

Cited By ~ 6

Author(s):

Lei He ◽

Andrew B. Kahng ◽

King Ho Tam ◽

Jinjun Xiong

Keyword(s):

Buffer Insertion ◽

Wire Sizing

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Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model

2007 International Conference on Mechatronics and Automation ◽

10.1109/icma.2007.4304112 ◽

2007 ◽

Cited By ~ 1

Author(s):

Chang Qi ◽

Gao-feng Wang ◽

Yue-hua Chen

Keyword(s):

Delay Model ◽

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

Wire Sizing

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A new approach to simultaneous buffer insertion and wire sizing

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643602 ◽

1997 ◽

Cited By ~ 20

Author(s):

Chu ◽

Wong

Keyword(s):

Buffer Insertion ◽

New Approach ◽

Wire Sizing

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Power-optimal simultaneous buffer insertion/sizing and wire sizing

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) ◽

10.1109/iccad.2003.159741 ◽

2003 ◽

Author(s):

Ruiming Li ◽

Dian Zhou ◽

Jin Liu ◽

Xuan Zeng

Keyword(s):

Buffer Insertion ◽

Wire Sizing

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Power-Optimal Simultaneous Buffer Insertion/Sizing and Uniform Wire Sizing for Single Long Wires

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1464537 ◽

2005 ◽

Author(s):

Ruiming Li ◽

Dian Zhou ◽

Jin Liu ◽

Xuan Zeng

Keyword(s):

Buffer Insertion ◽

Wire Sizing

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Optimal wire sizing and buffer insertion for low power and a generalized delay model

IEEE Journal of Solid-State Circuits ◽

10.1109/4.494206 ◽

1996 ◽

Vol 31 (3) ◽

pp. 437-447 ◽

Cited By ~ 117

Author(s):

J. Lillis ◽

Chung-Kuan Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

Wire Sizing

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Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511092 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jin-Tai Yan ◽

Shi-Qin Huang ◽

Zhi-Wei Chen

Keyword(s):

Obstacle Avoidance ◽

Steiner Tree ◽

Buffer Insertion ◽

Tree Construction ◽

Wire Sizing

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