wire sizing
Recently Published Documents


TOTAL DOCUMENTS

124
(FIVE YEARS 0)

H-INDEX

21
(FIVE YEARS 0)

2020 ◽  
pp. 223-232
Author(s):  
Bill Brooks ◽  
Sean White
Keyword(s):  

Author(s):  
Sean White
Keyword(s):  

2018 ◽  
Vol 17 (4) ◽  
pp. 1536-1548 ◽  
Author(s):  
Sandip Bhattacharya ◽  
Subhajit Das ◽  
Arnab Mukhopadhyay ◽  
Debaprasad Das ◽  
Hafizur Rahaman

Author(s):  
Bill Brooks ◽  
Sean White
Keyword(s):  

Author(s):  
Meng Liu ◽  
Zhiwei Zhang ◽  
Wenqin Sun ◽  
Donglin Wang
Keyword(s):  

2016 ◽  
Vol 26 (03) ◽  
pp. 1730002 ◽  
Author(s):  
A. Karthikeyan ◽  
P. S. Mallick

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.


2016 ◽  
pp. 2374-2378
Author(s):  
Chris Chu
Keyword(s):  

Author(s):  
Chung-Wei Lin ◽  
Lei Rao ◽  
Paolo Giusto ◽  
Joseph D'Ambrosio ◽  
Alberto L. Sangiovanni-Vincentelli

Sign in / Sign up

Export Citation Format

Share Document