Optimal wire sizing and buffer insertion for low power and a generalized delay model

J. Lillis;  Chung-Kuan Cheng; T.-T.Y. Lin

doi:10.1109/4.494206

Optimal wire sizing and buffer insertion for low power and a generalized delay model

IEEE Journal of Solid-State Circuits ◽

10.1109/4.494206 ◽

1996 ◽

Vol 31 (3) ◽

pp. 437-447 ◽

Cited By ~ 117

Author(s):

J. Lillis ◽

Chung-Kuan Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

Wire Sizing

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Optimal wire sizing and buffer insertion for low power and a generalized delay model

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480004 ◽

2002 ◽

Cited By ~ 65

Author(s):

J. Lillis ◽

C.-K. Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

Wire Sizing

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Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model

2007 International Conference on Mechatronics and Automation ◽

10.1109/icma.2007.4304112 ◽

2007 ◽

Cited By ~ 1

Author(s):

Chang Qi ◽

Gao-feng Wang ◽

Yue-hua Chen

Keyword(s):

Delay Model ◽

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

Wire Sizing

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Layout-aware gate-sizing and buffer insertion for low-power low-noise DSM circuits

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. ◽

10.1109/soc.2003.1241517 ◽

2004 ◽

Cited By ~ 1

Author(s):

A. Mukhejee ◽

R. Sankaranarayan ◽

K.R. Dusety

Keyword(s):

Low Power ◽

Low Noise ◽

Gate Sizing ◽

Buffer Insertion

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.766728 ◽

1999 ◽

Vol 18 (6) ◽

pp. 787-798 ◽

Cited By ~ 30

Author(s):

C.C.N. Chu ◽

D.F. Wong

Keyword(s):

Quadratic Programming ◽

Programming Approach ◽

Buffer Insertion ◽

Wire Sizing

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Buffer insertion and sizing under process variations for low power clock distribution

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95 ◽

10.1145/217474.217576 ◽

1995 ◽

Cited By ~ 37

Author(s):

Joe G. Xi ◽

Wayne W. M. Dai

Keyword(s):

Low Power ◽

Process Variations ◽

Clock Distribution ◽

Buffer Insertion

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Optimal non-uniform wire-sizing under the Elmore delay model

Proceedings of International Conference on Computer Aided Design ◽

10.1109/iccad.1996.568937 ◽

2002 ◽

Cited By ~ 14

Author(s):

Chung-Ping Chen ◽

Hai Zhou ◽

D.F. Wong

Keyword(s):

Delay Model ◽

Wire Sizing

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Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2006.884869 ◽

2007 ◽

Vol 26 (5) ◽

pp. 845-857 ◽

Cited By ~ 6

Author(s):

Lei He ◽

Andrew B. Kahng ◽

King Ho Tam ◽

Jinjun Xiong

Keyword(s):

Buffer Insertion ◽

Wire Sizing

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Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280900 ◽

1998 ◽

Cited By ~ 8

Author(s):

Unni Narayanan ◽

Peichen Pan ◽

C. L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

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A new approach to simultaneous buffer insertion and wire sizing

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643602 ◽

1997 ◽

Cited By ~ 20

Author(s):

Chu ◽

Wong

Keyword(s):

Buffer Insertion ◽

New Approach ◽

Wire Sizing

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Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708190 ◽

2002 ◽

Author(s):

U. Narayanan ◽

Peichen Pan ◽

C.L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

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