A performance-driven global routing algorithm with wire-sizing and buffer-insertion

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242) ◽

10.1109/apccas.1998.743673 ◽

2002 ◽

Author(s):

T. Deguchi ◽

T. Koide ◽

S. Wakabayashi

Keyword(s):

Routing Algorithm ◽

Global Routing ◽

Buffer Insertion ◽

Wire Sizing ◽

A Performance

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Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368586 ◽

2000 ◽

Cited By ~ 4

Author(s):

Takahiro Deguchi ◽

Tetsushi Koide ◽

Shin'ichi Wakabayashi

Keyword(s):

Global Routing ◽

Buffer Insertion ◽

Wire Sizing

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Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.720317 ◽

1998 ◽

Vol 17 (9) ◽

pp. 803-818 ◽

Cited By ~ 6

Author(s):

N. Togawa ◽

M. Yanagisawa ◽

T. Ohtsuki

Keyword(s):

Routing Algorithm ◽

Global Routing ◽

Technology Mapping ◽

A Performance

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Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835078 ◽

2002 ◽

Cited By ~ 2

Author(s):

T. Deguchi ◽

T. Koide ◽

S. Wakabayashi

Keyword(s):

Global Routing ◽

Buffer Insertion ◽

Wire Sizing

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A New Global Routing Algorithm For FPGAs

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629817 ◽

2005 ◽

Cited By ~ 2

Author(s):

Yao-Wen Chang ◽

S. Thakur ◽

Kai Zhu ◽

D.F. Wong

Keyword(s):

Routing Algorithm ◽

Global Routing

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A simultaneous placement and global routing algorithm for FPGAs

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 ◽

10.1109/iscas.1994.408843 ◽

2002 ◽

Cited By ~ 4

Author(s):

N. Togawa ◽

M. Sato ◽

T. Ohtsuki

Keyword(s):

Routing Algorithm ◽

Global Routing

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A Provably Good Global Routing Algorithm in Multilayer IC and MCM Layout Designs

Operations Research and Cyber-Infrastructure ◽

10.1007/978-0-387-88843-9_23 ◽

2009 ◽

pp. 443-454

Author(s):

Mohamed Saad ◽

Tamás Terlaky ◽

Anthony Vannelli ◽

Hu Zhang

Keyword(s):

Routing Algorithm ◽

Global Routing

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An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-13-5950-7_55 ◽

2019 ◽

pp. 670-681

Author(s):

Arindam Sinharay ◽

Subrata Das ◽

Pranab Roy ◽

Hafizur Rahaman

Keyword(s):

Steiner Tree ◽

Routing Algorithm ◽

Graphene Nanoribbon ◽

Global Routing

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.766728 ◽

1999 ◽

Vol 18 (6) ◽

pp. 787-798 ◽

Cited By ~ 30

Author(s):

C.C.N. Chu ◽

D.F. Wong

Keyword(s):

Quadratic Programming ◽

Programming Approach ◽

Buffer Insertion ◽

Wire Sizing

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Maple: A Simultaneous Technology Mapping, Placement, And Global Routing Algorithm For Field-programmable Gate Arrays

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629759 ◽

2005 ◽

Cited By ~ 7

Author(s):

N. Togawa ◽

M. Sato ◽

T. Ohtsuki

Keyword(s):

Routing Algorithm ◽

Field Programmable Gate Arrays ◽

Global Routing ◽

Technology Mapping ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2006.884869 ◽

2007 ◽

Vol 26 (5) ◽

pp. 845-857 ◽

Cited By ~ 6

Author(s):

Lei He ◽

Andrew B. Kahng ◽

King Ho Tam ◽

Jinjun Xiong

Keyword(s):

Buffer Insertion ◽

Wire Sizing

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