Effective analytical delay model for transistor sizing

2005 ◽  
Author(s):  
Zhaojun Wo ◽  
Israel Koren
Keyword(s):  
Delay Model ◽  
Transistor Sizing ◽  
Analytical Delay Model

scholarly journals Network Delays and Link Capacities in Application-Specific Wormhole NoCs

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-15 ◽  
Author(s):  
Zvika Guz ◽  
Isask'har Walter ◽  
Evgeny Bolotin ◽  
Israel Cidon ◽  
Ran Ginosar ◽  
...  
Keyword(s):  
Interconnection Networks ◽  
Packet Delay ◽  
Capacity Allocation ◽  
Delay Model ◽  
Capacity Assignment ◽  
Systems On Chip ◽  
Individual Capacity ◽  
On Chip ◽  
Analytical Delay Model ◽  
Application Specific

Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.

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