Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.
Latest Publications

TOTAL DOCUMENTS

329

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780387368

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Scheduler implementation in MP SoC design

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466148 ◽

2005 ◽

Cited By ~ 1

Author(s):

Youngchul Cho ◽

Sungjoo Yoo ◽

Kiyoung Choi ◽

N.-E. Zergainoh ◽

Ahmed Amine Jerraya

Download Full-text

Timing analysis considering temporal supply voltage fluctuation

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466532 ◽

2005 ◽

Cited By ~ 4

Author(s):

M. Hashimoto ◽

J. Yamaguchi ◽

T. Sato ◽

H. Onodera

Keyword(s):

Supply Voltage ◽

Timing Analysis ◽

Voltage Fluctuation

Download Full-text

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466238 ◽

2005 ◽

Cited By ~ 6

Author(s):

Lingfeng Li ◽

S. Goto ◽

T. Ikenaga

Keyword(s):

Deblocking Filter ◽

Parallel Memory ◽

Filter Architecture

Download Full-text

Sleep transistor sizing using timing criticality and temporal currents

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466531 ◽

2005 ◽

Cited By ~ 22

Author(s):

A. Ramalingam ◽

Bin Zhang ◽

D.Z. Pan ◽

A. Devgan

Keyword(s):

Transistor Sizing

Download Full-text

Analysis of buffered hybrid structured clock networks

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466137 ◽

2005 ◽

Author(s):

Yi Zou ◽

Qiang Zhou ◽

Yici Cai ◽

Xianlong Hong ◽

S.X.-D. Tan

Keyword(s):

Clock Networks

Download Full-text

Design and implementation of an SDH high-speed switch

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466606 ◽

2005 ◽

Author(s):

De Hui Zhang ◽

Quan Liang Zhao ◽

Jun Gang Han

Keyword(s):

High Speed ◽

Design And Implementation

Download Full-text

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466201 ◽

2005 ◽

Author(s):

Chanseok Hwang ◽

M. Pedram

Download Full-text

Stability analysis of active clock deskewing systems using a control theoretic approach

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466234 ◽

2005 ◽

Cited By ~ 2

Author(s):

V. Varghese ◽

T. Chen ◽

P. Young

Keyword(s):

Stability Analysis ◽

Theoretic Approach

Download Full-text

The development of high performance FFT IP cores through hybrid low power algorithmic methodology

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466224 ◽

2005 ◽

Cited By ~ 2

Author(s):

Wei Han ◽

A.T. Erdogan ◽

T. Arslan ◽

M. Hasan

Keyword(s):

Low Power ◽

High Performance ◽

Ip Cores

Download Full-text

Bridging fault testability of BDD circuits

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466155 ◽

2005 ◽

Cited By ~ 1

Author(s):

Junhao Shi ◽

G. Fey ◽

R. Drechsler

Keyword(s):

Bridging Fault

Download Full-text

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Scheduler implementation in MP SoC design

Timing analysis considering temporal supply voltage fluctuation

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Sleep transistor sizing using timing criticality and temporal currents

Analysis of buffered hybrid structured clock networks

Design and implementation of an SDH high-speed switch

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Stability analysis of active clock deskewing systems using a control theoretic approach

The development of high performance FFT IP cores through hybrid low power algorithmic methodology

Bridging fault testability of BDD circuits

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.
Latest Publications