scholarly journals Network Delays and Link Capacities in Application-Specific Wormhole NoCs

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-15 ◽  
Author(s):  
Zvika Guz ◽  
Isask'har Walter ◽  
Evgeny Bolotin ◽  
Israel Cidon ◽  
Ran Ginosar ◽  
...  
Keyword(s):  
Interconnection Networks ◽  
Packet Delay ◽  
Capacity Allocation ◽  
Delay Model ◽  
Capacity Assignment ◽  
Systems On Chip ◽  
Individual Capacity ◽  
On Chip ◽  
Analytical Delay Model ◽  
Application Specific

Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.

scholarly journals The TaPaSCo Open-Source Toolflow

2021 ◽  
Author(s):  
Carsten Heinz ◽  
Jaco Hofmann ◽  
Jens Korinth ◽  
Lukas Sommer ◽  
Lukas Weber ◽  
...  
Keyword(s):  
Open Source ◽  
System Integration ◽  
Design Space Exploration ◽  
Systems On Chip ◽  
Spatially Distributed ◽  
On Chip ◽  
Many Core ◽  
Hardware Designs ◽  
Application Specific

AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

scholarly journals 2D and 3D Based Network on Chip for a Stream of Data using Label Switching Technique

2019 ◽  
Vol 9 (1) ◽  
pp. 418-423
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Interconnection Networks ◽  
High Performance ◽  
Network On Chip ◽  
Label Switching ◽  
Systems On Chip ◽  
On Chip ◽  
2D And 3D ◽  
Reduction In Area

Universal interconnection networks are prime performance tailback for high performance SoCs (Systems-on-Chip). Since shrinking the size of the ICs (Integrated Circuits) is the main aim, NoC (Network-on-Chip), being a segmental and mountable design tactic is a propitious substitute to outmoded bus-mode architectures. NoC combined with 3D-Routers and label switching technique can guarantee low power consumption, QoS along with less latency. In the proposed work, 3D NoCs are proven to be more advantageous by achieving 39.9% reduction in Area, 1.7% reduction in Power Consumption, and 11.3% reduction in Memory usage.

scholarly journals Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 913 ◽  
Author(s):  
Sirine Mnejja ◽  
Yassine Aydi ◽  
Mohamed Abid ◽  
Salvatore Monteleone ◽  
Vincenzo Catania ◽  
...  
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Average Delay ◽  
Networks On Chip ◽  
Energy Profiles ◽  
Multi Stage ◽  
Systems On Chip ◽  
Viable Solution ◽  
On Chip ◽  
Scalable Communication

The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.

scholarly journals Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 10
Author(s):  
Jan Moritz Joseph ◽  
Dominik Ermel ◽  
Lennart Bamberg ◽  
Alberto García-Oritz ◽  
Thilo Pionteck
Keyword(s):  
Simulated Annealing ◽  
Cost Function ◽  
Linear Models ◽  
Nonlinear Models ◽  
General Purpose ◽  
Network Graph ◽  
Systems On Chip ◽  
On Chip ◽  
Core Mapping ◽  
Application Specific

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.

Adaptive multi-layer techniques for increased system dependability

2015 ◽  
Vol 57 (3) ◽  
Author(s):  
Lars Bauer ◽  
Jörg Henkel ◽  
Andreas Herkersdorf ◽  
Michael A. Kochte ◽  
Johannes M. Kühn ◽  
...  
Keyword(s):  
General Purpose ◽  
System Level ◽  
Coarse Grained ◽  
Common Goal ◽  
Fine Grained ◽  
Reconfigurable Processors ◽  
Systems On Chip ◽  
On Chip ◽  
Application Specific ◽  
Heterogeneous Mpsoc

AbstractAchieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner.In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, fine-grained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different

Application-specific multiprocessor Systems-on-Chip

2002 ◽  
Vol 33 (11) ◽  
pp. 891-898 ◽  
Author(s):  
Ahmed Amine Jerraya ◽  
Amer Baghdadi ◽  
Wander Cesário ◽  
Lovic Gauthier ◽  
Damien Lyonnard ◽  
...  
Keyword(s):  
Multiprocessor Systems ◽  
Systems On Chip ◽  
On Chip ◽  
Application Specific
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