transistor sizing
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2021 ◽  
Author(s):  
Bernardo Borges Sandoval ◽  
Leonardo Heitich Brendler ◽  
Alexandra L. Zimpeck ◽  
Fernanda L. Kastensmidt ◽  
Ricardo Reis ◽  
...  
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2021 ◽  
Vol 3 (3) ◽  
pp. 194-208
Author(s):  
P. Karthigaikumar

Transistor sizing is one the developing field in VLSI. Many researches have been conducted to achieve automatic transistor sizing which is a complex task due to its large design area and communication gap between different node and topology. In this paper, automatic transistor sizing is implemented using a combinational methods of Graph Convolutional Neural Network (GCN) and Reinforcement Learning (RL). In the graphical structure the transistor are represented as apexes and the wires are represented as boundaries. Reinforcement learning techniques acts a communication bridge between every node and topology of all circuit. This brings proper communication and understanding among the circuit design. Thus the Figure of Merit (FOM) is increased and the experimental results are compared with different topologies. It is proved that the circuit with prior knowledge about the system, performs well.


2021 ◽  
Author(s):  
Yaguang Li ◽  
Yishuang Lin ◽  
Meghna Madhusudan ◽  
Arvind Sharma ◽  
Sachin Sapatnekar ◽  
...  

2020 ◽  
Vol 10 (2) ◽  
pp. 17
Author(s):  
Leonardo Barboni

The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design.


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