Patterned overlays: thin silicon layer applied to glass waveguides

2011 ◽  
Author(s):  
Kristian E. Medri ◽  
Robert C. Gauthier
Keyword(s):  
Silicon Layer ◽  
Glass Waveguides ◽  
Thin Silicon

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

SOI SJ high voltage device with linear variable doping interface thin silicon layer

2012 ◽  
Vol 48 (5) ◽  
pp. 287 ◽  
Author(s):  
L.J. Wu ◽  
W.T. Zhang ◽  
M. Qiao ◽  
B. Zhang ◽  
Z.J. Li
Keyword(s):  
High Voltage ◽  
Silicon Layer ◽  
Thin Silicon

Thermal Transport in Novel Silicon Transistors

2004 ◽  
Author(s):  
Keivan Etessam-Yazdani ◽  
Wenjun Liu ◽  
Yizhang Yang ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Semiconductor Device ◽  
Silicon Layer ◽  
Phonon Transport ◽  
Interface Roughness ◽  
Strained Silicon ◽  
Boltzmann Transport ◽  
Strained Si ◽  
Thin Silicon ◽  
The Impact

This manuscript investigates the relevance and impact of nanoscale thermal phenomena in the state-of-the-art semiconductor device technologies such as: silicon-on-insulator (SOI), strained silicon, and tri-gate CMOS transistors. The experimental data and predictions for thin silicon layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in strained-Si/Ge bi-layer configuration are used to estimate the thermal resistance of the SOI, tri-gate, and strained-silicon-on-SiGe-on-insulator (SGOI) transistors, respectively. In particular, the impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the silicon layer at room temperature is investigated. In order to avoid the complexity of the BTE for predictions of the temperature distribution, Lumped Analytical (LA) models are introduced that are simple to implement and also adequate enough to capture the sub-continuum effects. It is concluded that the SOI, SGOI and tri-gate transistors are all susceptible to self-heating for very thin silicon device layers.

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