SOI SJ high voltage device with linear variable doping interface thin silicon layer

2012 ◽  
Vol 48 (5) ◽  
pp. 287 ◽  
Author(s):  
L.J. Wu ◽  
W.T. Zhang ◽  
M. Qiao ◽  
B. Zhang ◽  
Z.J. Li
Keyword(s):  
High Voltage ◽  
Silicon Layer ◽  
Thin Silicon

Thin silicon layer p-channel SOI/PSOI LDMOS with interface n+-islands for high voltage application

2014 ◽  
Vol 67 ◽  
pp. 1-7 ◽  
Author(s):  
Shengdong Hu ◽  
Zhi Zhu ◽  
Xinghe Wu ◽  
Jingjing Jin ◽  
Yinhui Chen
Keyword(s):  
High Voltage ◽  
Silicon Layer ◽  
Voltage Application ◽  
Thin Silicon

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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