Silicon dry etching profile control by RIE at room temperature for MEMS applications

2005 ◽  
Author(s):  
D. Vrtacnik ◽  
D. Resnik ◽  
U. Aljancic ◽  
M. Mozek ◽  
S. Amon
Keyword(s):  
Room Temperature ◽  
Dry Etching ◽  
Profile Control ◽  
Etching Profile

Dry Etching of GaN Using Reactive Ion Beam Etching and Chemically Assisted Reactive Ion Beam Etching

1997 ◽  
Vol 468 ◽  
Author(s):  
Jae-Won Lee ◽  
Hyong-Soo Park ◽  
Yong-Jo Park ◽  
Myong-Cheol Yoo ◽  
Tae-Il Kim ◽  
...  
Keyword(s):  
Room Temperature ◽  
Volume Fraction ◽  
Ion Beam ◽  
Etching Rate ◽  
Dry Etching ◽  
Ion Beam Etching ◽  
Etching Profile ◽  
Etching Parameters ◽  
Etching Selectivity ◽  
Reactive Ion Beam Etching

ABSTRACTDry etching characteristics of GaN using reactive ion beam etching (RIBE) were studied. Etching profile, etching rate and etching selectivity to a photoresist (PR) mask were investigated as a function of various etching parameters. Characteristics of chemically assisted reactive ion beam etching (CARIBE) and RIBE were compared at varied mixtures of CH4 and Cl2. A highly anisotropie etching profile with a smooth surface was obtained for tilted RIBE with Ch at room temperature. Etching selectivity to a PR was dramatically improved in RIBE and CARIBE when a volume fraction of CH4 to the mixture of CH4 and Ch was larger than 0.83.

Invited Paper Dry Etching Of Indium Phosphide At Room Temperature

1985 ◽  
Author(s):  
G. F. Doughty ◽  
C. L. Dargan ◽  
C. D. W. .. Wilkinson
Keyword(s):  
Indium Phosphide ◽  
Room Temperature ◽  
Dry Etching

scholarly journals The CORE Sequence: A Nanoscale Fluorocarbon-Free Silicon Plasma Etch Process Based on SF6/O2 Cycles with Excellent 3D Profile Control at Room Temperature

2020 ◽  
Vol 9 (2) ◽  
pp. 024002 ◽  
Author(s):  
Vy Thi Hoang Nguyen ◽  
Chantal Silvestre ◽  
Peixiong Shi ◽  
Roy Cork ◽  
Flemming Jensen ◽  
...  
Keyword(s):  
Room Temperature ◽  
Plasma Etch ◽  
The Core ◽  
Core Sequence ◽  
Free Silicon ◽  
Profile Control ◽  
3D Profile

Development of GaN and InGaN Gratings by Dry Etching

1997 ◽  
Vol 468 ◽  
Author(s):  
J. W. Lee ◽  
J. Hong ◽  
J. D. Mackenzie ◽  
C. R. Abernathy ◽  
S. J. Pearton ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dry Etching ◽  
Holographic Lithography ◽  
Periodic Gratings

ABSTRACTSub-micron periodic gratings with pitch ∼3,000Å were formed in GaN and InGaN using holographic lithography and room temperature ECR BCl3/N2 dry etching at moderate microwave (500W) and rf (100W) powers. The process produces uniform gratings without the need for elevated sample temperatures during the etch step.

Accurate Dry Etching with Fluorinated Gas for Two-dimensional Si Photonic Crystal

2000 ◽  
Vol 637 ◽  
Author(s):  
Chiharu Takahashi ◽  
Jun-Ichi Takahashi ◽  
Masaya Notomi ◽  
Itaru Yokohama
Keyword(s):  
Photonic Crystal ◽  
Room Temperature ◽  
High Selectivity ◽  
Photonic Band Gap ◽  
Electronic Devices ◽  
Dry Etching ◽  
Two Dimensional ◽  
Ecr Plasma ◽  
Etching Mask ◽  
Photonic Band

AbstractAnisortopic Si dry etching is usually carried out with chlorinated gases for electronic devices such as Si-LSIs. We had another look at Si dry etching with fluorinated gases in order to obtain an ideal air hole for two-dimensional Si photonic crystal. We simulated vertical Si etching, and showed the possibility that single crystal Si can be etched vertically with high selectivity to the etching mask using fluorinated gases. We investigated ECR etching with an SF6-CF4 mixture, and vertical Si etching was achieved at room temperature. High Si/Ni selectivity above 100 was also obtained. Two-dimensional Si photonic crystal with a photonic band gap between 1.25 and 1.51 μm was produced using SF6-CF4 ECR plasma and a thin Ni mask.

Evaluation of quartz dry etching profile for the PSM lithography performance

2005 ◽  
Author(s):  
Toru Komizo ◽  
Satoru Nemoto ◽  
Yosuke Kojima ◽  
Takashi Ohshima ◽  
Takashi Yoshii ◽  
...  
Keyword(s):  
Dry Etching ◽  
Etching Profile

Failure Analysis and Process Improvement for Through Silicon Via Interconnects

2009 ◽  
Vol 1156 ◽  
Author(s):  
Bivragh Majeed ◽  
Marc Van Cauwenberghe ◽  
Deniz Sabuncuoglu Tezcan ◽  
Philippe Soussan
Keyword(s):  
Failure Analysis ◽  
Process Improvement ◽  
Etching Rate ◽  
Dry Etching ◽  
Etching Process ◽  
Thickness Variation ◽  
Silicon Etching ◽  
Soft Landing ◽  
Etching Profile ◽  
Etching Parameters

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Formation of Long Wavelength InP Laser MESAS

1993 ◽  
Vol 300 ◽  
Author(s):  
F. Ren ◽  
S. J. Pearton ◽  
B. Tseng ◽  
J. R. Lothian ◽  
C. Constantine
Keyword(s):  
Elevated Temperature ◽  
Etch Rate ◽  
Room Temperature ◽  
Plasma Chemistry ◽  
Dry Etching ◽  
Pattern Transfer ◽  
Process Step ◽  
Long Wavelength ◽  
Low Degree ◽  
Etched Surface

ABSTRACTNarrow (1 μm), deep (3.5 μm) laser mesas have been formed on 2”φ InP wafers using stepper lithography and dry etching techniques for both dielectric and semiconductor patterning. Contrast enhancement techniques produce excellent edge acuity and vertical sidewalls on the initial photoresist lines. Pattern transfer to the underlying SiO2 regrowth mask is achieved by ECR SF6/Ar dry etching at 1 mTorr and –100V, conditions which also retain the verticality of the mesa. The semiconductor is etched using an ECR Cl2/CH4/H2/Ar discharge at 0.3 mTorr and –80V, with the sample held at ∼ 150°C. The etch rate under these conditions is ∼1 μm/min, with a selectivity of ≥10:1 for the semiconductor over the dielectric mask. The smooth etched surface and low degree of damage make this process ideal for epitaxial regrowth. The uniformity of each process step is also acceptable (≤7%). Comparison of the elevated temperature Cl2/CH4/H2/Ar mixture with the more conventional room temperature CH4/H2 plasma chemistry will be given.

A systematic dry etching process for profile control of quantum dots and nanoconstrictions

2007 ◽  
Vol 38 (8-9) ◽  
pp. 823-827 ◽  
Author(s):  
Madnarski Sutikno ◽  
Uda Hashim ◽  
Zul Azhar Zahid Jamal
Keyword(s):  
Quantum Dots ◽  
Dry Etching ◽  
Etching Process ◽  
Profile Control
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