Evaluation of quartz dry etching profile for the PSM lithography performance

2005 ◽  
Author(s):  
Toru Komizo ◽  
Satoru Nemoto ◽  
Yosuke Kojima ◽  
Takashi Ohshima ◽  
Takashi Yoshii ◽  
...  
Keyword(s):  
Dry Etching ◽  
Etching Profile

Silicon dry etching profile control by RIE at room temperature for MEMS applications

2005 ◽  
Author(s):  
D. Vrtacnik ◽  
D. Resnik ◽  
U. Aljancic ◽  
M. Mozek ◽  
S. Amon
Keyword(s):  
Room Temperature ◽  
Dry Etching ◽  
Profile Control ◽  
Etching Profile

Dry Etching of GaN Using Reactive Ion Beam Etching and Chemically Assisted Reactive Ion Beam Etching

1997 ◽  
Vol 468 ◽  
Author(s):  
Jae-Won Lee ◽  
Hyong-Soo Park ◽  
Yong-Jo Park ◽  
Myong-Cheol Yoo ◽  
Tae-Il Kim ◽  
...  
Keyword(s):  
Room Temperature ◽  
Volume Fraction ◽  
Ion Beam ◽  
Etching Rate ◽  
Dry Etching ◽  
Ion Beam Etching ◽  
Etching Profile ◽  
Etching Parameters ◽  
Etching Selectivity ◽  
Reactive Ion Beam Etching

ABSTRACTDry etching characteristics of GaN using reactive ion beam etching (RIBE) were studied. Etching profile, etching rate and etching selectivity to a photoresist (PR) mask were investigated as a function of various etching parameters. Characteristics of chemically assisted reactive ion beam etching (CARIBE) and RIBE were compared at varied mixtures of CH4 and Cl2. A highly anisotropie etching profile with a smooth surface was obtained for tilted RIBE with Ch at room temperature. Etching selectivity to a PR was dramatically improved in RIBE and CARIBE when a volume fraction of CH4 to the mixture of CH4 and Ch was larger than 0.83.

Failure Analysis and Process Improvement for Through Silicon Via Interconnects

2009 ◽  
Vol 1156 ◽  
Author(s):  
Bivragh Majeed ◽  
Marc Van Cauwenberghe ◽  
Deniz Sabuncuoglu Tezcan ◽  
Philippe Soussan
Keyword(s):  
Failure Analysis ◽  
Process Improvement ◽  
Etching Rate ◽  
Dry Etching ◽  
Etching Process ◽  
Thickness Variation ◽  
Silicon Etching ◽  
Soft Landing ◽  
Etching Profile ◽  
Etching Parameters

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Erratum: Dry etching process for fabrication of optoelectronic gratings in III-V substrates

1992 ◽  
Vol 28 (3) ◽  
pp. 338
Author(s):  
A.S. Gozdz ◽  
J.A. Shelburne ◽  
R.S. Robinson ◽  
C.C. Chang
Keyword(s):  
Dry Etching ◽  
Etching Process

scholarly journals Low-temperature smoothing method of scalloped DRIE trench by post-dry etching process based on SF6 plasma

2020 ◽  
Vol 8 (1) ◽  
Author(s):  
Jin Soo Park ◽  
Dong-Hyun Kang ◽  
Seung Min Kwak ◽  
Tae Song Kim ◽  
Jung Ho Park ◽  
...  
Keyword(s):  
Low Temperature ◽  
Dry Etching ◽  
Smoothing Method ◽  
Etching Process

Low Bias Voltage Dry Etching of InP by Inductively Coupled Plasma Using SiCl4/Ar

1998 ◽  
Vol 37 (Part 1, No. 12A) ◽  
pp. 6655-6656 ◽  
Author(s):  
Akihiro Matsutani ◽  
Fumio Koyama ◽  
Kenichi Iga
Keyword(s):  
Bias Voltage ◽  
Inductively Coupled Plasma ◽  
Dry Etching ◽  
Inductively Coupled

scholarly journals Formation of SiO2 hard mask using dry etching and nanosphere lithography

2020 ◽  
Vol 1697 ◽  
pp. 012188
Author(s):  
E A Vyacheslavova ◽  
I A Morozov ◽  
D A Kudryashov ◽  
A S Gudovskikh
Keyword(s):  
Nanosphere Lithography ◽  
Dry Etching ◽  
Hard Mask

scholarly journals Fabrication of Ultranarrow Nanochannels with Ultrasmall Nanocomponents in Glass Substrates

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 775
Author(s):  
Hiroki Kamai ◽  
Yan Xu
Keyword(s):  
Electron Beam ◽  
Electron Beam Lithography ◽  
Dry Etching ◽  
Dissimilar Material ◽  
Glass Substrates ◽  
Nanofluidic Devices ◽  
Fundamental Research ◽  
Fine Glass ◽  
Physical Phenomena

Nanofluidics is supposed to take advantage of a variety of new physical phenomena and unusual effects at nanoscales typically below 100 nm. However, the current chip-based nanofluidic applications are mostly based on the use of nanochannels with linewidths above 100 nm, due to the restricted ability of the efficient fabrication of nanochannels with narrow linewidths in glass substrates. In this study, we established the fabrication of nanofluidic structures in glass substrates with narrow linewidths of several tens of nanometers by optimizing a nanofabrication process composed of electron-beam lithography and plasma dry etching. Using the optimized process, we achieved the efficient fabrication of fine glass nanochannels with sub-40 nm linewidths, uniform lateral features, and smooth morphologies, in an accurate and precise way. Furthermore, the use of the process allowed the integration of similar or dissimilar material-based ultrasmall nanocomponents in the ultranarrow nanochannels, including arrays of pockets with volumes as less as 42 zeptoliters (zL, 10−21 L) and well-defined gold nanogaps as narrow as 19 nm. We believe that the established nanofabrication process will be very useful for expanding fundamental research and in further improving the applications of nanofluidic devices.

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