Failure analysis of wafer-level reliability testing failure

1999 ◽  
Author(s):  
Chong K. Oh ◽  
Soh P. Neo ◽  
Jian H. Bi ◽  
Zong M. Wu ◽  
Lian C. Goh ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Reliability Testing ◽  
Wafer Level

Unique Autoclave Stress Induced Failure Mechanism

2005 ◽  
Author(s):  
John Butchko ◽  
Bruce T. Gillette
Keyword(s):  
Corrosion Rate ◽  
Grain Boundary ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Corrosion ◽  
Corrosion Mechanism ◽  
Reliability Testing ◽  
Process Change ◽  
Transistor Reliability ◽  
Pass Through

Abstract Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.

Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal

2012 ◽  
Author(s):  
Jason H. Lagar ◽  
Rudolf A. Sia
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Vital Role ◽  
Fault Isolation ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Coating Removal ◽  
Customer Returns ◽  
Preparation Techniques ◽  
Mechanical Defect

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Failure Analysis of Polysilicon Micromirror Arrays

2002 ◽  
Author(s):  
Jeremy A. Walraven ◽  
Edward I. Cole ◽  
Danelle M. Tanner ◽  
Seethambal S. Mani ◽  
Ernest J. Garcia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Optical Switching ◽  
Failure Modes ◽  
Reliability Testing ◽  
Processing Technologies ◽  
Optical Signals ◽  
Home Entertainment ◽  
Micromirror Arrays ◽  
Spectrometer System ◽  
Potential Use

Abstract Surface micromachined micromirror technologies are being employed for various commercial and government applications. One application of micromirror technologies in the commercial sector can be found in Digital Light Projection (DLP™) systems used for theater and home entertainment centers. DLP™ systems developed by Texas Instruments uses DMD™ technology (Digital Mirror Device), an array of micromirrors, to project light onto a screen [1]. This technology is also used by Infocus™ projection systems and widescreen tabletop televisions [2]. Here, the micromirrors act as individual pixels, reflecting light onto the screen with high ¡§digital¡¨ resolution. The most recent application of surface micromachined micromirror technology is optical switching [3], which uses micromirrors to switch optical signals from fiber to fiber for lightwave telecommunications [4]. Companies such as Lucent have fabricated entire optical micromirror switching systems based on their Microstar™ technology [5]. For government applications, surface micromachined micromirror arrays have been developed for potential use in a spectrometer system planned for NASA's Next Generation Space Telescope (NGST) [6]. Various processing technologies are used to fabricate surface micromachined micromirrors. The micromirror arrays developed by TI and Lucent [1,4] uses metal for their structural and reflective components. Micromirrors fabricated at Sandia National Laboratories use the SUMMiT™ (Sandia's Ultra-planar MEMS Multi-level Technology) process with metal deposited on the surface of mechanical polysilicon components to reflect light. Optical micromirror arrays designed and fabricated at Sandia for potential use in the NGST have undergone reliability testing and failure analysis. This paper will discuss the failure modes found in these micromirrors after reliability testing. Suggestions and corrective actions for improvements in device performance will also be discussed.

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