Effect of interface traps parameters on admittance characteristics of the MIS (metal-insulator-semiconductor) tunnel structures

2016 ◽  
Author(s):  
Jakub Jasiński ◽  
Andrzej Mazurak ◽  
Bogdan Majkusiak
Keyword(s):  
Interface Traps ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor

Importance of minority carrier response in accurate characterization of Ge metal-insulator-semiconductor interface traps

2009 ◽  
Vol 106 (4) ◽  
pp. 044506 ◽  
Author(s):  
Noriyuki Taoka ◽  
Toyoji Yamamoto ◽  
Masatomi Harada ◽  
Yoshimi Yamashita ◽  
Naoharu Sugiyama ◽  
...  
Keyword(s):  
Minority Carrier ◽  
Interface Traps ◽  
Semiconductor Interface ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor

Nature of interface traps in Ge metal-insulator-semiconductor structures with GeO2 interfacial layers

2011 ◽  
Vol 109 (8) ◽  
pp. 084508 ◽  
Author(s):  
Noriyuki Taoka ◽  
Wataru Mizubayashi ◽  
Yukinori Morita ◽  
Shinji Migita ◽  
Hiroyuki Ota ◽  
...  
Keyword(s):  
Interface Traps ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Interfacial Layers ◽  
Semiconductor Structures

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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