GERMANIUM–BASED METAL–INSULATOR–SEMICONDUCTOR TRANSISTORS AS A WAY OF FURTHER DEVELOPMENT OF CMOS TECHNOLOGY

2016 ◽  
1993 ◽  
Vol 316 ◽  
Author(s):  
Fereydoon Namavar ◽  
N. Kalkhoran ◽  
A. Cremins ◽  
S. Vernon

ABSTRACTArsenic precipitates can be formed in GaAs using arsenic implantation and annealing, thereby producing very high resistivity (surface or buried) GaAs layers. Arsenic-implanted materials are similar to low-temperature (LT) GaAs:As buffer layers grown by molecular beam epitaxy (MBE) which are used for eliminating side- and backgating problems in GaAs circuits. Arsenic implantation is not only a simple and economical technique for device isolation but also can improve the quality of individual devices. Through surface passivation, arsenic implantation can reduce gate-to-drain leakage in and enhance the breakdown voltage of GaAs-based metal semiconductor field-effect transistors (MESFETs) and high electron mobility transistors (HEMTs). High resistivity thin surface layers may be used as gate insulators for GaAs-based metal insulator semiconductor (MIS) FETs, leading to the development of a novel GaAs-based complementary metal insulator semiconductor (CMIS) technology like advanced Si-based complementary metal oxide semiconductor (CMOS) technology but with higher radiation hardness and operational speed.


2017 ◽  
Author(s):  
Varun Bheemireddy

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>


2004 ◽  
Vol 38 (12) ◽  
pp. 1390-1393
Author(s):  
V. A. Terekhov ◽  
A. N. Man’ko ◽  
E. N. Bormontov ◽  
V. N. Levchenko ◽  
S. Yu. Trebunskikh ◽  
...  

1993 ◽  
Vol 32 (Part 2, No. 9A) ◽  
pp. L1200-L1202 ◽  
Author(s):  
Kunio Ichino ◽  
Toshikazu Onishi ◽  
Yoichi Kawakami ◽  
Shizuo Fujita ◽  
Shigeo Fujita

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