Design and development of wafer-level near-infrared micro-camera

2015 ◽  
Author(s):  
John W. Zeller ◽  
Caitlin Rouse ◽  
Harry Efstathiadis ◽  
Pradeep Haldar ◽  
Nibir K. Dhar ◽  
...  
2018 ◽  
Author(s):  
Chun Haur Khoo

Abstract Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.


1996 ◽  
Vol 6 (2) ◽  
pp. 69-75 ◽  
Author(s):  
Maryam I. Daneshvar ◽  
Guillermo A. Casay ◽  
Gabor Patonay ◽  
Malgorzata Lipowska ◽  
Lucjan Strekowski ◽  
...  

Author(s):  
Vaidyanathan Kripesh ◽  
Vempati Srinivas Rao ◽  
Aditya Kumar ◽  
Gaurav Sharma ◽  
Khong Chee Houe ◽  
...  

2012 ◽  
Vol 52 (4) ◽  
pp. 1175-1179 ◽  
Author(s):  
Ryosuke Kojima ◽  
Hideo Takakura ◽  
Takeaki Ozawa ◽  
Yukio Tada ◽  
Tetsuo Nagano ◽  
...  

2013 ◽  
Author(s):  
Ashok K. Sood ◽  
Robert A. Richwine ◽  
Gopal Pethuraja ◽  
Yash R. Puri ◽  
Je-Ung Lee ◽  
...  

2012 ◽  
Vol 125 (4) ◽  
pp. 1213-1217 ◽  
Author(s):  
Ryosuke Kojima ◽  
Hideo Takakura ◽  
Takeaki Ozawa ◽  
Yukio Tada ◽  
Tetsuo Nagano ◽  
...  

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 002015-002049
Author(s):  
G. Fresquet

3D Integration of miniaturized systems at wafer level generates new needs of metrology and defects inspection for the control of TSV geometries, temporary wafer bonding, wafer thinning, via interconnects technology and of wafer/die stacks. In this paper we demonstrate the capabilities of a versatile optical measurement system combining several microscopy and interferometry techniques in the visible and near infrared wavelength range. I. INTRODUCTION AND BACKGROUND ALL roadmaps predict a large spread of 3D heterogeneous integration technologies for the fabrication of miniaturized systems in the coming years1. Beside a large development of new fabrication processes, 3D integration generates new challenges in terms of metrology and defects inspection for wafer/die bonding, thinning and interconnection processes as well as for 3D architectures. Adaptation and/or combination of existing techniques and the development of new techniques become necessary in order to perform non destructive, fast and inspections or quantitative measurements on large area wafers with high lateral and vertical resolutions. In this work we describe results obtained with an optical system combining several microscopy and interferometry techniques.


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