Characterization of semiconductor device structures using contactless electromodulation

1995 ◽  
Author(s):  
Fred H. Pollak ◽  
Wojciech Krystek ◽  
M. Leibovitch ◽  
S. Moneger ◽  
Hao Qiang ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
Device Structures

TEM Sample Fabrication of Sub 22 nm Three-Dimensional Test Structures

2013 ◽  
Author(s):  
James J. Demarest
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Three Dimensional ◽  
Manufacturing Plants ◽  
Transmission Electron ◽  
Device Structures ◽  
Device Integration ◽  
The One ◽  
Device Technology

Abstract With the 14nm technology node becoming a reality at today's state-of-the-art semiconductor manufacturing plants and the 10nm node actively being planned for, device structures have shrunk well beyond the minimum conventional transmission electron microscope (TEM) sample thickness: 50-100nm. This paper addresses the challenges in TEM sample preparation of sub 22nm three-dimensional test structures. As semiconductor device technology continues to shrink and become more complicated with the addition of three-dimensional device integration, unique sample preparation challenges will continue to arise. This opens the door to novel solutions for these problems like the one presented in this paper: an issue that arose where TEM projection effects interfered with proper characterization of a finFET test structure.

scholarly journals Non-destructive characterization of extended crystalline defects in confined semiconductor device structures

Nanoscale ◽  
2018 ◽  
Vol 10 (15) ◽  
pp. 7058-7066 ◽  
Author(s):  
Andreas Schulze ◽  
Libor Strakos ◽  
Tomas Vystavel ◽  
Roger Loo ◽  
Antoine Pacco ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
Quantitative Characterization ◽  
Crystalline Defects ◽  
Device Structures ◽  
Non Destructive ◽  
Non Destructive Characterization

Non-destructive and quantitative characterization of crystalline defects: understanding the formation and distribution of defects in nanoscale semiconductor device structures.

Applications of SIMS to electronic materials and devices

1992 ◽  
Vol 50 (2) ◽  
pp. 1682-1683
Author(s):  
S.F. Corcoran
Keyword(s):  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Profile Analysis ◽  
Semiconductor Industry ◽  
Small Diameter ◽  
Depth Resolution ◽  
Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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