Remote plasma etching reactors: Modeling and experiment

Author(s):  
Shashank C. Deshmukh
Keyword(s):  
2016 ◽  
Vol 113 (26) ◽  
pp. 7026-7034 ◽  
Author(s):  
Klaus Bartschat ◽  
Mark J. Kushner

Electron collisions with atoms, ions, molecules, and surfaces are critically important to the understanding and modeling of low-temperature plasmas (LTPs), and so in the development of technologies based on LTPs. Recent progress in obtaining experimental benchmark data and the development of highly sophisticated computational methods is highlighted. With the cesium-based diode-pumped alkali laser and remote plasma etching of Si3N4 as examples, we demonstrate how accurate and comprehensive datasets for electron collisions enable complex modeling of plasma-using technologies that empower our high-technology–based society.


2007 ◽  
Vol 84 (1) ◽  
pp. 37-41 ◽  
Author(s):  
Ronald Hellriegel ◽  
Matthias Albert ◽  
Bernd Hintze ◽  
Hubert Winzig ◽  
J.W. Bartha

1998 ◽  
Vol 16 (4) ◽  
pp. 2047-2056 ◽  
Author(s):  
B. E. E. Kastenmeier ◽  
P. J. Matsuo ◽  
G. S. Oehrlein ◽  
J. G. Langan

2020 ◽  
Vol 127 (16) ◽  
pp. 169902
Author(s):  
Vincent Renaud ◽  
Camille Petit-Etienne ◽  
Jean-Paul Barnes ◽  
Jérémie Bisserier ◽  
Olivier Joubert ◽  
...  

2018 ◽  
Vol 282 ◽  
pp. 126-131
Author(s):  
Kurt Wostyn ◽  
Karine Kenis ◽  
Hans Mertens ◽  
Adrian Vaisman Chasin ◽  
Andriy Hikavyy ◽  
...  

For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH3/NF3remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si0.75Ge0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.


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