Insulated gate depletion mode and accumulation mode field effect transistors on InP fabricated by electron beam lithography

1984 ◽  
Vol 2 (2) ◽  
pp. 123
Author(s):  
Richard Scheps
Keyword(s):  
Electron Beam ◽  
Electron Beam Lithography ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Accumulation Mode ◽  
Mode Field

Accumulation mode field-effect transistors for improved sensitivity in nanowire-based biosensors

2012 ◽  
Vol 100 (21) ◽  
pp. 213703 ◽  
Author(s):  
David J. Baek ◽  
Juan P. Duarte ◽  
Dong-Il Moon ◽  
Chang-Hoon Kim ◽  
Jae-Hyuk Ahn ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Accumulation Mode ◽  
Mode Field

Influence of electron-beam lithography exposure current level on the transport characteristics of graphene field effect transistors

2016 ◽  
Vol 119 (12) ◽  
pp. 124502 ◽  
Author(s):  
Sangwoo Kang ◽  
Hema C. P. Movva ◽  
Atresh Sanne ◽  
Amritesh Rai ◽  
Sanjay K. Banerjee
Keyword(s):  
Electron Beam ◽  
Electron Beam Lithography ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Current Level

Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography

2003 ◽  
Vol 42 (Part 1, No. 6B) ◽  
pp. 4142-4146 ◽  
Author(s):  
Yongxun Liu ◽  
Kenichi Ishii ◽  
Toshiyuki Tsutsumi ◽  
Meishoku Masahara ◽  
Hidenori Takashima ◽  
...  
Keyword(s):  
Electron Beam ◽  
Metal Oxide ◽  
Electron Beam Lithography ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Double Gate

Recent Progress in Downsizing FeFETs for Fe-NAND Application

2011 ◽  
Vol 1337 ◽  
Author(s):  
Le Van Hai ◽  
Mitsue Takahashi ◽  
Shigeki Sakai
Keyword(s):  
Electron Beam ◽  
Electron Beam Lithography ◽  
Inductively Coupled Plasma ◽  
Field Effect ◽  
Recent Progress ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Electrical Characteristics ◽  
Gate Stacks ◽  
Inductively Coupled

ABSTRACTSub-micrometer ferroelectric-gate field-effect transistors (FeFETs) of 0.56 μm and 0.50 μm gate lengths were successfully fabricated for Fe-NAND cells. Gate stacks of the FeFETs were Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. The gate stacks were formed by electron beam lithography and inductively coupled plasma reactive ion etching (ICP-RIE). Ti and SiO2 hard masks were used for the 0.56 μm- and 0.50 μm-gate FeFETs, respectively, in the ICP-RIE process. Steep SBT sidewalls with the angle of 85° were obtained by using the SiO2 hard masks while 76° sidewalls were shown using Ti hard masks. All fabricated FeFETs showed good electrical characteristics. Drain current hysteresis showed larger memory windows than 0.95 V when the gate voltages were swung between 1±5 V. The FeFETs showed stable endurance behaviors over 108 program/erase cycles. Drain current retention properties of the FeFETs were good so that the drain current on/off ratios did not show practical changes after 3 days.

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