Characterization of low permittivity (low-k) polymeric dielectric films for low temperature device integration

2002 ◽  
Vol 20 (3) ◽  
pp. 1149-1153 ◽  
Author(s):  
S. Sivoththaman ◽  
R. Jeyakumar ◽  
L. Ren ◽  
A. Nathan
Keyword(s):  
Low Temperature ◽  
Dielectric Films ◽  
Device Integration ◽  
Low Permittivity ◽  
Low K

Electrical Characterization of Sub-30nm Gatelength SOI MOSFETs

2004 ◽  
Author(s):  
Terence Kane ◽  
Michael P. Tenney
Keyword(s):  
Electrical Characterization ◽  
Dielectric Films ◽  
Atomic Force ◽  
Soi Devices ◽  
Low K

Abstract Atomic Force Probe (AFP) techniques are well suited for the electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k interlevel dielectric films. This paper discusses the use of these techniques on sub-30nm gatelength SOI MOSFETs.

Nondestructive in Situ Characterization of Molecular Structures at the Surface and Buried Interface of Silicon-Supported Low-k Dielectric Films

2015 ◽  
Vol 119 (4) ◽  
pp. 1736-1746 ◽  
Author(s):  
John N. Myers ◽  
Xiaoxian Zhang ◽  
Jeff Bielefeld ◽  
Qinghuang Lin ◽  
Zhan Chen
Keyword(s):  
Molecular Structures ◽  
Dielectric Films ◽  
In Situ Characterization ◽  
Low K

Synthesis and Characterization of Methyltriethoxysilane Based Low Permittivity (Low-k) Polymeric Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Z. Gu ◽  
R. Jeyakumar ◽  
S. Sivoththaman ◽  
A. Nathan
Keyword(s):  
Dielectric Constant ◽  
Spin Coating ◽  
Base Material ◽  
Curing Temperature ◽  
Curing Conditions ◽  
Annealing Temperatures ◽  
Polymeric Dielectrics ◽  
Low Permittivity ◽  
Low K

AbstractA low-permittivity (low-k) polymeric material has been synthesized using methyltriethoxysilane as base material. The films were reproduceably deposited, by spin-coating on Si wafers with a uniform thickness in the range of 0.3-0.5μm depending on speed. The parameters for spin coating (spin speed and spin time etc.,) have been optimized. The effects of various curing conditions on the structural and dielectric properties have been studied. Fourier Transform Infrared Spectroscopy (FTIR) shows prominent peaks of Si-CH3 stretch and Si-O stretch modes. Test structures on silicon were fabricated to measure the dielectric constant (k) of the material. The values of k were found to be in the range of 2.6-1.2 for annealing temperatures 150°C-450°C. The dielectric constant decreases as the curing temperature increases.

Chemical and Morphological Characterization of Low-k Dielectric Films Deposited From Hexamethyldisiloxane and Ethylene RF Glow Discharges

2010 ◽  
Vol 7 (12) ◽  
pp. 1022-1029 ◽  
Author(s):  
Anna Maria Coclite ◽  
Antonella Milella ◽  
Fabio Palumbo ◽  
Francesco Fracassi ◽  
Riccardo d'Agostino
Keyword(s):  
Morphological Characterization ◽  
Dielectric Films ◽  
Glow Discharges ◽  
Low K

Characterization of Low Temperature SiNx Films for 3D/2.5D-IC TSV

2015 ◽  
Vol 135 (7) ◽  
pp. 733-738 ◽  
Author(s):  
Yasushi Kobayashi ◽  
Yoshihiro Nakata ◽  
Tomoji Nakamura ◽  
Mayumi B. Takeyama ◽  
Masaru Sato ◽  
...  
Keyword(s):  
Low Temperature

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

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