In-situ moire measurement of adhesive flip-chip bonded assembly under thermal cycling condition

Author(s):  
Suk-Jin Ham ◽  
Woon-Seong Kwon ◽  
Kyung-Wook Paik ◽  
Soon-Bok Lee
2012 ◽  
Vol 52 (7) ◽  
pp. 1441-1444 ◽  
Author(s):  
Yunsung Kim ◽  
Hyelim Choi ◽  
Hyoungjoo Lee ◽  
Dongjun Shin ◽  
Jinhan Cho ◽  
...  

2007 ◽  
Vol 539-543 ◽  
pp. 368-373 ◽  
Author(s):  
Cheng Jin ◽  
Ji Tai Niu ◽  
Shi Yu He ◽  
Hong Bin Geng ◽  
G. Long

In this paper, the micro-damage mechanisms of 5A06 Al alloy weld joints have been studied under the condition of constant load and cyclic thermal load. The mechanical performance variation of the base material and its weld joint are analyzed and compared. Microstructure analysis reveals that the main damage mechanism in weld joints is the interior voids nucleation and growth. The voids distribution and evolution govern the damage process. Test results also show most fractures occur at HAZ near the welding fusion line. The development of these voids results in the performance deterioration of the weld joints under thermal cycling condition.


Author(s):  
Yoshihiko Kanda ◽  
Kunihiro Zama ◽  
Yoshiharu Kariya ◽  
Takao Mikami ◽  
Takaya Kobayashi ◽  
...  

The effect of viscoelasticity of underfill on the reliability analysis of flip-chip package by using FEA has been investigated in this study. The analytical result on thermal warpage of a package is different depending on whether the underfill is assumed to be elastic or viscoelastic. The difference is prominent in materials with low Tg, specifically during the cooling process. The viscoelastic effect of the underfill on the fatigue life of the solder bumps is also appears in materials with low Tg, and the predicted fatigue life of a package is about twice as short if the underfill is assumed to be elastic instead of viscoelastic. Thus, the differences in the assumption regarding the viscoelastic properties of the underfill affect the reliability analysis of the packages under thermal cycling condition using FEA.


2019 ◽  
Vol 141 (4) ◽  
Author(s):  
John H. Lau

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.


2006 ◽  
Vol 326-328 ◽  
pp. 525-528 ◽  
Author(s):  
Samson Yoon ◽  
Seung Min Cho ◽  
Yuri Lee ◽  
Bong Tae Han

A unique interferometric system utilizing thermal-conduction loading is developed and implemented to investigate the effect of ramp rates of accelerated test profiles on the thermal deformation of flex package assemblies. The system provides extreme ramp rates to simulate the thermal shock condition with a temperature control much finer than the conventional convection based system can provide. The in-plane and out-of-plane displacements of the flex package are documented through moiré interferometry and Twyman/Green interferometry, respectively. Deformation measured under a thermal shock condition is compared with that under the conventional thermal cycling condition to assess the effect of ramp rates on package deformation. The comparison reveals that a low ramp rate of typical accelerated thermal cycling (ATC) tests causes significant reduction in the maximum level of elastic energy in the package assembly.


Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.


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