Flip-Chip Assembly of RF MEMS for Microwave Hybrid Circuitry

2005 ◽  
Author(s):  
Daniel J. Hyman ◽  
Roger Kuroda
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Rf Mems ◽  
Phase Shifters ◽  
Lessons Learned ◽  
High Yield ◽  
Pure Gold ◽  
Mems Devices ◽  
Large Area ◽  
Flip Chip Assembly

XCom Wireless is a small business specializing in RF MEMS-enabled tunable filters and phase shifters for next-generation communications systems. XCom has developed a high-yielding flip-chip assembly and packaging technique for implementing RF MEMS devices into fully-packaged chip-scale hybrid integrated circuitry for radio and microwave frequency applications through 25 GHz. This paper discusses the packaging approach employed, performance and reliability aspects, and lessons learned. The packaging is similar to a hybrid module approach, with discrete RF MEMS component dies flip-chipped into larger packages containing large-area integrated passives. The first level of interconnect is a pure gold flip chip for high yield strength and reliability with small dies. The use of first-level flip-chip and second-level BGAs allows the extremely large bandwidth MEMS devices to maintain high performance characteristics.

RF-MEMS Components and Networks for High-Performance Reconfigurable Telecommunication and Wireless Systems

2012 ◽  
Vol 81 ◽  
pp. 65-74 ◽  
Author(s):  
Jacopo Iannacci ◽  
Giuseppe Resta ◽  
Paola Farinelli ◽  
Roberto Sorrentino
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Low Cost ◽  
Impedance Matching ◽  
Phase Shifters ◽  
Rf Systems ◽  
Mems Technology ◽  
And Performance ◽  
Rf Performance

MEMS (MicroElectroMechanical-Systems) technology applied to the field of Radio Frequency systems (i.e. RF-MEMS) has emerged in the last 10-15 years as a valuable and viable solution to manufacture low-cost and very high-performance passive components, like variable capacitors, inductors and micro-relays, as well as complex networks, like tunable filters, reconfigurable impedance matching networks and phase shifters, and so on. The availability of such components and their integration within RF systems (e.g. radio transceivers, radars, satellites, etc.) enables boosting the characteristics and performance of telecommunication systems, addressing for instance a significant increase of their reconfigurability. The benefits resulting from the employment of RF-MEMS technology are paramount, being some of them the reduction of hardware redundancy and power consumption, along with the operability of the same RF system according to multiple standards. After framing more in detail the whole context of RF MEMS technology, this paper will provide a brief introduction on a typical RF-MEMS technology platform. Subsequently, some relevant examples of lumped RF MEMS passive elements and complex reconfigurable networks will be reported along with their measured RF performance and characteristics.

MEMS-Enabled Smart Beam-Steering Antennas

2014 ◽  
pp. 183-203
Author(s):  
Hadi Mirzajani ◽  
Habib Badri Ghavifekr ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Beam Steering ◽  
Smart Antennas ◽  
Phase Shifters ◽  
Rapid Rate ◽  
Mems Devices ◽  
Batch Fabrication ◽  
Mems Technology ◽  
Smart Beam

In recent years, Microelectromechanical Systems (MEMS) technology has seen a rapid rate of evolution because of its great potential for advancing new products in a broad range of applications. The RF and microwave devices and components fabricated by this technology offer unsurpassed performance such as near-zero power consumption, high linearity, and cost effectiveness by batch fabrication in respect to their conventional counterparts. This chapter aims to give an in-depth overview of the most recently published methods of designing MEMS-based smart antennas. Before embarking into the different techniques of beam steering, the concept of smart antennas is introduced. Then, some fundamental concepts of MEMS technology such as micromachining technologies (bulk and surface micromachining) are briefly discussed. After that, a number of RF MEMS devices such as switches and phase shifters that have applications in beam steering antennas are introduced and their operating principals are completely explained. Finally, various configurations of MEMS-enabled beam steering antennas are discussed in detail.

Solder Mobility for High-Yield Self-Aligned Flip-Chip Assembly

2017 ◽  
Author(s):  
Yves Martin ◽  
Swetha Kamlapurkar ◽  
Jae-Woong Nah ◽  
Nathan Marchack ◽  
Tymon Barwicz
Keyword(s):  
Flip Chip ◽  
High Yield ◽  
Flip Chip Assembly

scholarly journals Direct roll transfer printed silicon nanoribbon arrays based high-performance flexible electronics

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Ayoub Zumeit ◽  
Abhishek Singh Dahiya ◽  
Adamos Christou ◽  
Dhayalan Shakthivel ◽  
Ravinder Dahiya
Keyword(s):  
Flexible Electronics ◽  
High Performance ◽  
Printed Electronics ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Single Step ◽  
High Yield ◽  
Transfer Printing ◽  
Large Area ◽  
Direct Printing

AbstractTransfer printing of high mobility inorganic nanostructures, using an elastomeric transfer stamp, is a potential route for high-performance printed electronics. Using this method to transfer nanostructures with high yield, uniformity and excellent registration over large area remain a challenge. Herein, we present the ‘direct roll transfer’ as a single-step process, i.e., without using any elastomeric stamp, to print nanoribbons (NRs) on different substrates with excellent registration (retaining spacing, orientation, etc.) and transfer yield (∼95%). The silicon NR based field-effect transistors printed using direct roll transfer consistently show high performance i.e., high on-state current (Ion) >1 mA, high mobility (μeff) >600 cm2/Vs, high on/off ratio (Ion/off) of around 106, and low hysteresis (<0.4 V). The developed versatile and transformative method can also print nanostructures based on other materials such as GaAs and thus could pave the way for direct printing of high-performance electronics on large-area flexible substrates.

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

High performance and large area flip-chip bonded AlGaN/GaN MODFETs

2002 ◽  
Author(s):  
B.J. Thibeault ◽  
B.P. Keller ◽  
P. Fini ◽  
U.K. Mishra ◽  
C. Nguyen ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Large Area

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

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