System and Package Level Thermal Optimization of Power Amplifier Modules With Application in Wireless Communication

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
David Lutz
Keyword(s):  
Power Amplifier ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Peak Temperature ◽  
System Level ◽  
Specific Test ◽  
Baseline Design ◽  
Thermal Optimization ◽  
Solid Ground ◽  
Test Conditions

Increased functionality of microelectronic packages for commercial applications leads to the necessity of identifying packaging solutions with high standards for thermal performance, during its functioning lifetime as well as during various test conditions. A detailed numerical analysis examines the thermal characteristics of a power amplifier module for time division multiple access (TDMA), using commercially available software. The increasing trend in power levels and densities leads to the need of design thermal optimization, either at module level or system level. Under specific test conditions, the thermal performance of the module degrades gradually; therefore, alternative test designs are investigated for thermal performance optimization. Initial study focuses on assessing the thermal performance of a baseline design. The peak temperature reaches 144°C, about 60°C temperature increase over the reference temperature. The peak temperature value is below the limit of 150°C. Further investigation focuses on several systems level designs, by incorporating individual test contactors between the DUT and load board or with conductive elastomers or pedestal solid ground slug for thermal performance enhancement. The peak temperatures are calculated in this case for the system being exposed to the ambient at 85°C. The results indicate that the test design with solid ground slug provides the best thermal performance, ∼ 5% better than the other designs. The small difference between the first two designs (with individual contactors and separate solid ground slug with conductive elastomer) resides in the fact that the elastomer has a small thickness (0.25mm), thus a low thermal resistance (based on thermal conductivity greater than 1W/mK), with minimal impact on the overall thermal performance of the TDMA under current test conditions. The temperature difference between the top section of the contactor designs with the CBC pin/copper block/pedestal is small; in spite of this, the high temperature reached by the individual CBC pins induces possible failures in the elastomer. The designs with pedestal and solid ground slugs have a notable advantage over the design with individual contactors, due to no moving parts within the elastomer, being more robust. The peak temperature reached by the module under the best/worst testing scenarios varies by ∼ 4–5%.

Thermal Assessment of a Power Amplifier Module in Wireless Handsets

2002 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Power Amplifier ◽  
Thermal Performance ◽  
Thermal Characteristics ◽  
Initial Study ◽  
Sensitivity Study ◽  
Thermal Design ◽  
Peak Temperature ◽  
Baseline Design ◽  
High Standards ◽  
Commercial Applications

Increased functionality of microelectronic packages for commercial applications leads to the necessity of identifying packaging solutions with high standards for thermal performance. A detailed numerical analysis examines the thermal characteristics of a power amplifier module for time division multiple access (TDMA), using commercially available software. The increasing trend in power levels and densities leads to the need of design thermal optimization, either at the module level or at the system (module board stack-up) level. Several designs are investigated for thermal performance and the best thermal design is identified. Initial study focuses on assessing the thermal performance of a baseline design. The peak temperature reaches 144°C, about 60°C temperature increase over the reference temperature. The peak temperature value is slightly below the limit of 150°C, and is calculated based on the optimal (temperature constant) heat sink scenario attached to the bottom face of the module. Several alternatives are investigated, by modifying the thermal via array structure and Cu plating thickness. The increase in copper plating from 0.025 mm to 0.05 mm (1 to 2 mils) has the largest impact on module’s thermal performance. The addition of solder material and radio board increases by almost 50% the overall thermal resistance, hence the estimated peak temperatures reached by the heat stages would exceed the limit. A detailed sensitivity study was completed to assess the importance of each element in the module-board stack-up. Finally, a comprehensive experimental study was completed to validate the numerical simulation. The results indicate that the error between measurements and simulation range between 5–8%.

System-Level Transient Thermal Analysis for Performance Optimization of High Power Microelectronics

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
H. S. Chen
Keyword(s):  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Optimal Operation ◽  
System Level ◽  
Main Concern ◽  
Efficient Operation ◽  
Normal Test ◽  
Transient Thermal ◽  
Short Time

The increasing trend in power levels and densities leads to the need of design thermal optimization, at either module or system level. A numerical study using finite-volume software was conducted to model the transient thermal behavior of a system including a package dissipating large amounts of power over short time durations. The system is evaluated by choosing the appropriate heat sink for the efficient operation of the device under 100W of constant powering, also to enhance the thermal performance of the enclosure/box containing the test stack-up. The intent of the study is to provide a meaningful understanding and prediction of the high transient powering scenarios. The study focuses on several powering and system design scenarios, identifying the main issues encountered during a normal device operation. The power source dissipates 100W for 2 seconds then is cooled for another 2 seconds. This thermal cycle is likely to occur several times during a normal test-up, and it is the main concern of the manufacturers not to exceed a limit temperature during the device testing operation. The transient trend is further extrapolated analytically to extract the steady state peak temperature values, in order to maintain the device peak temperatures below 120°C. The benefit of the study is related to the possibility to extract the maximum/minimum temperatures for a real test involving a large number of heating-cooling cycles, yet maintaining the initial and peak temperatures within a certain range, for the optimal operation of the device. The flow and heat transfer fields are thoroughly investigated. By using a combination of numerical and analytical study, the thermal performance of the device undergoing infinity of periodic thermal cycles is further predicted.

System Level Thermal Performance Evaluation of New Inverted Exposed Pad Packages for Automotive Applications

2006 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Automotive Applications ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel 54 lead SOIC (with inverted exposed Cu pad) packages for automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rjhs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, a comparison with a different exposed pad package is made. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package. Several cases are evaluated in the paper, with an emphasis on the superior thermal performance of new packages for automotive applications.

Thermal Performance Optimization of Radio Frequency Packages for Wireless Communication

2004 ◽  
Vol 126 (4) ◽  
pp. 429-434 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A three-dimensional conjugate numerical study was conducted to evaluate the thermal performance of gallium arsenic die packaged in quad flat no-lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: (1) one for standard operating parameters and (2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5 °C (or 119 °C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186 °C (or 125 °C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126 °C (66 °C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe, and additional board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy versus solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an infrared microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Performance Optimization of RF Packages for Wireless Communication

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a new family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186°C (or 125°C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126°C (66°C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy vs. solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an Infrared (IR) Microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001635-001655
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Worst Case ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.

Steady-State and Transient Thermal Performance Optimization of Power Automotive Modules

2009 ◽  
Author(s):  
Victor Chiriac
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
System Level ◽  
Main Concern ◽  
Thermal Impact ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Transient Thermal

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of power packages for automotive applications. The automotive industry deals on a daily basis with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of IC incorporation into a system module, for present and future product development. Several packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal impact of the thicker lead frame and die attach material on the overall thermal behavior is evaluated. The main concern is exceeding the thermal budget at an external ambient temperature of 85°C, specific for the relatively extreme automotive operating environments. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ∼106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ∼260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. When the isothermal boundary is attached to package bottom, peak temperature drops by 20% after 40 ms. Additional system level with multiple optimized packages placed on a custom PCB is evaluated numerically and experimentally, placing an emphasis on the superior thermal performance of this new class of power packages for automotive applications. The optimized numerical model approximates closely the empirical results (121–126°C vs. 127.5°C), within 1–2%.

New Hybrid Methodology for the Development of MEMS Multivariable Sensors

2001 ◽  
Author(s):  
Emily J. Pryputniewicz ◽  
John P. Angelosanto ◽  
Gordon C. Brown ◽  
Cosme Furlong ◽  
Ryszard J. Pryputniewicz
Keyword(s):  
Process Control ◽  
Microelectromechanical Systems ◽  
Absolute Pressure ◽  
Single Chip ◽  
Specific Test ◽  
Mems Sensor ◽  
Test Conditions ◽  
Mems Technology ◽  
Functional Operation ◽  
Hybrid Methodology

Abstract Using recent advances in microelectromechanical systems (MEMS) technology, a new multivariable sensor was developed. This MEMS sensor, capable of measuring temperature, absolute pressure, and differential pressure on a single chip, is particularly suitable for applications in process control industry. However, functional operation of the sensor depends on validation of its performance under specific test conditions. We have developed a hybrid methodology, based on analysis and measurements, that allows such validation. In this paper, the MEMS multivariable sensor is described, the hybrid methodology is outlined, and its use is illustrated with representative results.

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