Thermal-Electrical Co-Optimization of Block-Level Floorplanning in 3D Integrated Circuits

2009 ◽  
Author(s):  
Ankur Jain ◽  
Syed Alam ◽  
Scott Pozder ◽  
Robert E. Jones
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Integrated Circuit ◽  
Thermal Design ◽  
Maximum Temperature ◽  
Design Tools ◽  
Design Constraint ◽  
Trade Offs ◽  
Block Level ◽  
3D Integrated Circuits

While the stacking of multiple strata to produce 3D integrated circuits improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge due to the increased power density. There is a need for design tools to understand and optimize the trade-off between electrical and thermal design at the device and block level. This paper presents results from thermal-electrical co-optimization for block-level floorplanning in a multi-die 3D integrated circuit. A method for temperature computation based on linearity of the governing energy equation is presented. This method is shown to be faster and more accurate than previously used resistance-network based approaches and full-scale FEM simulations. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimize both the maximum temperature and the interconnect length. Results outline the various trade-offs between thermal and electrical considerations. It is shown that co-optimization of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Constraints placed by the 3D IC manufacturing process on design are outlined, showing that the cheapest manufacturing options may not result in optimal electrical and thermal design. In particular, the wafer-on-wafer bonding process requires the two die to be identical, which results in a severe design constraint, particularly on the thermal goal due to the overlap of high power density blocks. Results presented in this work highlight the need for thermal and electrical co-design in multistrata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D integrated circuits.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

scholarly journals Maximum Temperature Detection System for Integrated Circuits

2015 ◽  
Vol 66 (2) ◽  
pp. 79-84
Author(s):  
Maciej Frankiewicz ◽  
Andrzej Kos
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Absolute Temperature ◽  
Maximum Temperature ◽  
Dynamic Frequency Scaling ◽  
Temperature Detection ◽  
Measurement Results ◽  
Power Management System ◽  
Dynamic Frequency

Abstract The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

scholarly journals Thermal management of the through silicon vias in 3-D integrated circuits

2019 ◽  
Vol 23 (4) ◽  
pp. 2157-2162
Author(s):  
Kang-Jia Wang ◽  
Chu-Xia Hua ◽  
Hong-Chang Sun
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Design Guidelines ◽  
Thermal Design ◽  
Through Silicon Via ◽  
Through Silicon Vias ◽  
Factors Affecting ◽  
Two Factors ◽  
Circuit Integration ◽  
Silicon Vias

The through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit integration. However, its size and the property of the filled-materials are two factors affecting the thermal behavior of the integrated circuits. In this paper, we design 3-D integrated circuits with different through silicon via models and analyze the effect of different material-filled through silicon vias, aspect ratio and thermal conductivity of the dielectric on the steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for through silicon vias in 3-D integrated circuits.

Thermal Analysis of 3D ICs With TSVs Placement Optimization

2019 ◽  
Author(s):  
Zongqing Ren ◽  
Ayed Alqahtani ◽  
Nader Bagherzadeh ◽  
Jaeho Lee
Keyword(s):  
Integrated Circuits ◽  
Power Distribution ◽  
Peak Temperature ◽  
Signal Delay ◽  
Placement Optimization ◽  
3D Ics ◽  
Trade Offs ◽  
3D Integrated Circuits ◽  
High Thermal Resistance ◽  
Silicon Vias

Abstract While 3D integrated circuits (3D ICs) offer a great enhancement in performance, the increased power density, nonuniform power distribution and high thermal resistance pose significant thermal management challenges. Thermal through-silicon-vias (TTSVs) are TSVs that do not carry signal but facilitate heat transfer across stacked dies. The use of TTSVs occupies extra space and extends the distance between IC blocks leading to an increase in signal delay. The trade-offs between the temperature and wirelength are evident in the TTSV placement. In this paper, we propose a hierarchical approach to optimize the floorplan of a 3D Nehalem-based multicore processor. The floorplan of a single core is optimized using simulated annealing (SA)-based algorithm and the floorplan of the entire 3D IC is generated based on the symmetric operation. Our simulation results show that the peak temperature decreases with the TTSV area overhead and the wirelength strongly depends on the TTSV placement. Compared to the SA-optimized floorplan with no TTSVs, the SA-optimized floorplans with TTSV offer 6–15 °C more reduction in peak temperature while keeping the wirelength increase from 10 % to 40 % at 2–20 % TTSV area overheads. We also evaluate the effects of anisotropic thermal transport in TTSVs and show that the lateral thermal conductivity of TTSV has a significant impact on the peak temperature of 3D ICs.

scholarly journals Thermal management of the hotspots in 3-D integrated circuits

2018 ◽  
Vol 22 (4) ◽  
pp. 1685-1690 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Cui-Ling Li ◽  
Guo-Dong Wang ◽  
Hong-Wei Zhu
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Vertical Integration ◽  
Integrated Circuit ◽  
Design Guidelines ◽  
Thermal Design ◽  
Micro Channel ◽  
Through Silicon Vias ◽  
Microchannel Cooling ◽  
Silicon Vias

Vertical integration for microelectronics possesses significant challenges due to its fast dissipation of heat generated in multiple device planes. This paper focuses on thermal management of a 3-D integrated circuit, and micro-channel cooling is adopted to deal with the 3-D integrated circuitthermal problems. In addition, thermal through-silicon vias are also used to improve the capacity of heat trans-mission. It is found that combination of microchannel cooling and thermal through-silicon vias can remarkably alleviate the hotspots. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3-D integrated circuits.

Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Nick Vo ◽  
Trent Uehling ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Electrical Current ◽  
Thermal Design ◽  
3D Ic ◽  
Thermal Models ◽  
3D Ics ◽  
And Performance

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

scholarly journals Thermal management of three-dimensional integrated circuits with special structures

2021 ◽  
pp. 109-109
Author(s):  
Kang-Jia Wang ◽  
Cui-Ling Li
Keyword(s):  
Temperature Distribution ◽  
Integrated Circuits ◽  
Heat Source ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Numerical Approach ◽  
Optimal Structure ◽  
Maximum Temperature ◽  
Three Dimensional Integrated Circuit

Different stacked structures affect greatly the temperature distribution of a three-dimensional integrated circuit(3-D IC), and an optimal structure is much needed to reduce the maximal temperature. This paper suggests a numerical approach to such structures with different heat source distributions. The results show that an optimal stacked structure can reduce the maximum temperature by 8.7?C.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

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