Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Nick Vo ◽  
Trent Uehling ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Electrical Current ◽  
Thermal Design ◽  
3D Ic ◽  
Thermal Models ◽  
3D Ics ◽  
And Performance

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

Fabrication of 3D-IC Interposers

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001295-001321
Author(s):  
John T. Keech ◽  
Garret Piech ◽  
Scott Pollard
Keyword(s):  
Integrated Circuit ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Cost Savings ◽  
Cost Effective ◽  
Quality Parameters ◽  
Substrate Material ◽  
3D Ic ◽  
And Performance ◽  
Three Dimensional Integrated Circuit

Interposer fabrication has gained a lot of attention in the area of three-dimensional integrated circuit (3D-IC) integration. Glass has many properties that make it well suited for interposer substrates, such as adjustable coefficient of thermal expansion, advantaged electrical properties and unique forming processes. Furthermore, glass based solutions can also provide significant cost advantages in substrate material, via formation, and subsequent processing. In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer substrates. Leveraging the ability to create through-glass-via (TGV) substrates in as-formed 100 μm thick precision glass, with a pristine surface, can avoid the need for back grinding and polishing operations. This has the potential to eliminate several manufacturing steps for polishing and thinning, while providing associated cost savings. Significant progress has been made in demonstration of TGV technology. Fully populated wafers with 100,000s of through or blind holes (≥ 25 μm diameter) are fabricated today, and 10–20 μm diameters are in development. We will report on important quality parameters measured on TGV wafers and positive implications with respect to product quality and strength. The ability to leverage industry metallization techniques and performance characteristics will also be reported. Finally, we will discuss opportunities to leverage cost-effective glass interposer solutions.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

scholarly journals Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Chi-Jih Shih ◽  
Chih-Yao Hsu ◽  
Chun-Yi Kuo ◽  
James Li ◽  
Jiann-Chyi Rau ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Test Time ◽  
3D Ic ◽  
Test Cost ◽  
Test Access Mechanism ◽  
3D Ics ◽  
The Cost ◽  
Test Schedule ◽  
Total Test

Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions:soft-die modeandhard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

scholarly journals Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages

Energies ◽  
2020 ◽  
Vol 13 (12) ◽  
pp. 3054
Author(s):  
Konstantin O. Petrosyants ◽  
Nikita I. Ryabov
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Software Tool ◽  
Thermal Design ◽  
Circuit Board ◽  
Processing Unit ◽  
Processor Time ◽  
3D Ic ◽  
Central Processing

The problem of thermal modeling of modern three-dimensional (3D) integrated circuit (IC) systems in packages (SiPs) is discussed. An effective quasi-3D (Q3D) approach of thermal design is proposed taking into account the specific character of 3D IC stacked multilayer constructions. The fully-3D heat transfer equation for global multilayer construction is reduced to the set of coupled two-dimensional (2D) equations for separate construction layers. As a result, computational difficulties, processor time, and RAM volume are significantly reduced, while accuracy can be provided. A software tool, Overheat-3D-IC, was developed on the base of the generalized Q3D package numerical model. For the first time, the global 3D thermal performances across the modern integrated circuit/through-silicon via/ball grid array (IC-TSV-BGA) and multi-chip (MC)-embedded printed circuit board (PCB) packages were simulated. A ten times decrease of central processing unit (CPU) time was achieved as compared with the 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature TMAX determination for different types of packages was not more than 10–20%.

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Leila Choobineh ◽  
Jared Jones ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Resistance ◽  
High Speed ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermal Design ◽  
Electrical Performance ◽  
Physical Parameters ◽  
Interconnect Delay ◽  
3D Ics

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

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