Thermal Analysis of 3D ICs With TSVs Placement Optimization

2019 ◽  
Author(s):  
Zongqing Ren ◽  
Ayed Alqahtani ◽  
Nader Bagherzadeh ◽  
Jaeho Lee
Keyword(s):  
Integrated Circuits ◽  
Power Distribution ◽  
Peak Temperature ◽  
Signal Delay ◽  
Placement Optimization ◽  
3D Ics ◽  
Trade Offs ◽  
3D Integrated Circuits ◽  
High Thermal Resistance ◽  
Silicon Vias

Abstract While 3D integrated circuits (3D ICs) offer a great enhancement in performance, the increased power density, nonuniform power distribution and high thermal resistance pose significant thermal management challenges. Thermal through-silicon-vias (TTSVs) are TSVs that do not carry signal but facilitate heat transfer across stacked dies. The use of TTSVs occupies extra space and extends the distance between IC blocks leading to an increase in signal delay. The trade-offs between the temperature and wirelength are evident in the TTSV placement. In this paper, we propose a hierarchical approach to optimize the floorplan of a 3D Nehalem-based multicore processor. The floorplan of a single core is optimized using simulated annealing (SA)-based algorithm and the floorplan of the entire 3D IC is generated based on the symmetric operation. Our simulation results show that the peak temperature decreases with the TTSV area overhead and the wirelength strongly depends on the TTSV placement. Compared to the SA-optimized floorplan with no TTSVs, the SA-optimized floorplans with TTSV offer 6–15 °C more reduction in peak temperature while keeping the wirelength increase from 10 % to 40 % at 2–20 % TTSV area overheads. We also evaluate the effects of anisotropic thermal transport in TTSVs and show that the lateral thermal conductivity of TTSV has a significant impact on the peak temperature of 3D ICs.

Silicon Interposer Featuring Novel Electrical and Optical TSVs

2012 ◽  
Author(s):  
Paragkumar A. Thadesar ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
System Level ◽  
Performance Improvements ◽  
Fine Pitch ◽  
3D Integrated Circuits ◽  
Photonic Interconnects ◽  
Silicon Vias

Three-dimensional (3D) integrated circuits (ICs) yield system level performance improvements by providing high-bandwidth communication as well as opportunity for heterogeneous integration. It is envisioned that an area array of 3D stacked ICs can be interconnected using dense fine-pitch electrical and photonic interconnects on a silicon interposer. This paper presents a mechanically robust “thick” silicon interposer with novel electrical through-silicon vias (TSVs) and optical TSVs. The novel electrical TSVs described include polymer-clad TSVs and polymer-embedded vias. An advantage of using thick silicon interposer is that microchannels can be integrated in the thick silicon interposer to transfer a coolant to the 3D ICs with interlayer microfluidic heat sink or for the direct integration of a microfluidic heat-sink in the silicon interposer. However, as the thickness of silicon interposer increases, TSV electrical parasitics increase. Moreover, the coefficient of thermal expansion (CTE) mismatch between the copper TSV and silicon causes reliability issues. To reduce TSV capacitance as well as to reduce TSV stresses, polymer-clad electrical TSVs were fabricated. Using the same photodefinable polymer used for the cladding of electrical TSVs, optical TSVs were fabricated and characterized.

scholarly journals System-on-chip testing

2019 ◽  
Author(s):  
Παναγιώτης Γεωργίου
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Rectangle Packing ◽  
3D Ics ◽  
Systems On Chip ◽  
Self Test ◽  
Chip Testing ◽  
On Chip ◽  
Silicon Vias ◽  
Access Mechanisms

Διανύουμε ήδη την εποχή του "Ίντερνετ των Πραγμάτων". Οι κοινές συσκευές που χρησιμοποιούμε καθημερινά, συνδέονται μεταξύ τους και γίνονται "εξυπνότερες" με ραγδαίους ρυθμούς. Σε κάθε τέτοια συσκευή βρίσκεται ένα Σύστημα σε Ολοκληρωμένο (Systems-On-Chip ή SoC). Το SoC εξελίσσεται συνεχώς, για να ικανοποιηθούν οι συνεχώς αυξανόμενες απαιτήσεις της νέας εποχής. Τα τρι-διάστατα ολοκληρωμένα κυκλώματα (three-dimensional integrated circuits - 3D-ICs) είναι μια υποσχόμενη λύση για να ικανοποιήσουν τις απαιτήσεις τις νέας εποχής και φαίνεται να εξασφαλίζουν τη συνέχιση του Νόμου του Moore στο άμεσο μέλλον. Τα 3D-ICs πετυχαίνουν υψηλότερη πυκνότητα πυλών και καλύτερη απόδοση από τα συμβατικά SoC και μειώνουν το κόστος διασύνδεσης και κατανάλωσης. Πρόσφατα, οι κατασκευαστικές εταιρείες ολοκληρωμένων συστημάτων κυκλοφόρησαν προϊόντα βασισμένα σε 3D-ICs. Η έρευνα αυτή εστιάζει στην ανάπτυξη νέων αρχιτεκτονικών μηχανισμού πρόσβασης ελέγχου (Test Access Mechanisms - TAMs) και νέων μεθόδων χρονοπρογραμματισμού ελέγχου ορθής λειτουργίας για 3D-SoCs, οι οποίες εκμεταλλεύονται την υψηλή ταχύτητα που προσφέρουν οι ειδικές κάθετες διασυνδέσεις μέσω-πυριτίου (Through Silicon Vias - TSVs), ενώ η κατανάλωση ισχύος και η θερμότητα πρέπει να διατηρηθούν κάτω από ορισμένα επίπεδα. Εισάγουμε μία νέα αρχιτεκτονική TAM για 3D SoCs, η οποία ελαχιστοποιεί το χρόνο ελέγχου ορθής λειτουργίας, το πλήθος των TSVs και τις γραμμές της αρχιτεκτονικής TAM που χρησιμοποιούνται για να μεταφερθούν τα δεδομένα ελέγχου. Ο χρονοπρογραμματισμός του ελέγχου ορθής λειτουργίας υπολογίζεται από μία αποδοτική μέθοδο χρονικής πολυπλεξίας και μία πολύ αποδοτική μέθοδο βελτιστοποίησης που βασίζεται στους αλγορίθμους rectangle-packing και simulated-annealing. Πειραματικά αποτελέσματα δείχνουν έως και 9.6 φορές εξοικονόμηση στο χρόνο ελέγχου με την προτεινόμενη μέθοδο, ειδικά κάτω από αυστηρά όρια για την κατανάλωση ισχύος και τη θερμότητα. Η προηγούμενη μέθοδος είναι συμβατή μόνο με TAMs που βασίζονται σε αρτηρίες (buses), οι οποίες απαιτούν διασυνδέσεις μεγάλου μήκους και πολλά buffers σε κάθε επίπεδο του 3D-IC, επομένως δεν καταφέρνουν να εκμεταλλευτούν πλήρως τις υψηλές συχνότητες των TSVs. Προτείνουμε μία νέα αρχιτεκτονική TAM βασισμένη στη χρονική πολυπλεξία, που χρησιμοποιεί σειριακές αλυσίδες (daisy-chains) για να ξεπεράσουμε τους περιορισμούς της προηγούμενης μεθόδου. Η μέθοδος αυτή προσφέρει μεγαλύτερα κέρδη όσον αφορά το χρόνο ελέγχου ορθής λειτουργίας και το κόστος διασύνδεσης. Η έρευνα αυτή εστιάζει στη βελτίωση ανίχνευσης σφαλμάτων συσκευών βασιζόμενων σε επεξεργαστή. Οι ολοένα αυξανόμενες απαιτήσεις της αγοράς για υψηλότερη υπολογιστική απόδοση σε μικρότερο κόστος και χαμηλότερη κατανάλωση ισχύος, οδηγεί τους κατασκευαστές στην ανάπτυξη νέων μικροεπεξεργαστών, που εισάγουν νέες προκλήσεις στον έλεγχο συσκευών βασιζόμενων σε επεξεργαστή. Η ανάγκη ελέγχου των συσκευών αυτών κατά τη διάρκεια της κανονικής τους λειτουργίας, επιβάλλουν τη συμπληρωματική χρήση μεθόδων ελέγχου που δεν επηρεάζουν τη λειτουργία, όπως ο «αυτοέλεγχος βασισμένος σε λογισμικό» (Software-Based Self-Test - SBST). Οι περισσότερες τεχνικές SBST στοχεύουν μόνο το μοντέλο σφαλμάτων stuck-at, που δεν αρκεί για την ανίχνευση πολλών σφαλμάτων. Επίσης, οι τεχνικές SBST απαιτούν εκτενή ανθρώπινη ενασχόληση με μεγάλους χρόνους ανάπτυξης των προγραμμάτων ελέγχου. Επιπλέον, περιλαμβάνουν την κοστοβόρα, από άποψη υπολογιστική ισχύος, εξομοίωση σφαλμάτων SoCs με εκατομμύρια πύλες για εκατομμύρια κύκλους ρολογιού, χρησιμοποιώντας πολλαπλά μοντέλα σφαλμάτων και εξειδικευμένους λειτουργικούς εξομοιωτές. Εισάγουμε την πρώτη μέθοδο που δεν μεροληπτεί υπέρ κάποιου συγκεκριμένου μοντέλου σφαλμάτων. Η μέθοδος αυτή προσφέρει σύντομο χρόνο δημιουργίας προγραμμάτων ελέγχου, υπό αυστηρό περιορισμό στο χρόνο ελέγχου ορθής λειτουργίας και στο μέγεθος των προγραμμάτων ελέγχου. Τα προγράμματα ελέγχου αξιολογούνται από μία νέα αποδοτική πιθανοτική μέθοδο SBST, εκμεταλλευόμενη την αρχιτεκτονική του επεξεργαστή, καθώς και τη netlist του επεξεργαστή σε επίπεδο πυλών που έχει προκύψει από σύνθεση. Η προτεινόμενη μετρική που βασίζεται στα output deviations είναι πολύ γρήγορη καθώς δεν απαιτεί τη χρονοβόρα διαδικασία της εξομοίωσης σφαλμάτων και μπορεί να εφαρμοστεί σε οποιαδήποτε μέθοδο που βασίζεται στην τεχνική SBST.

scholarly journals Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

ETRI Journal ◽  
2014 ◽  
Vol 36 (6) ◽  
pp. 931-941 ◽  
Author(s):  
Kyungin Cho ◽  
Cheoljon Jang ◽  
Jong-wha Chong
Keyword(s):  
Integrated Circuits ◽  
Network Design ◽  
Mesh Network ◽  
Through Silicon Vias ◽  
3D Integrated Circuits ◽  
Silicon Vias

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

2011 ◽  
Vol 28 (1) ◽  
pp. 53-62 ◽  
Author(s):  
Benjamin Backes ◽  
Colin McDonough ◽  
Larry Smith ◽  
Wei Wang ◽  
Robert E. Geer
Keyword(s):  
Integrated Circuits ◽  
Through Silicon Vias ◽  
3D Integrated Circuits ◽  
Silicon Vias

High Speed Signal Transmission using Through-Si Vias and Coplanar Waveguides in a 3D IC Test Structure

2013 ◽  
Vol 2013 (1) ◽  
pp. 000228-000232
Author(s):  
Min Xu ◽  
Robert Geer ◽  
Pavel Kabos ◽  
Thomas Wallis
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
High Speed ◽  
Signal Transmission ◽  
Coplanar Waveguides ◽  
Scattering Parameter ◽  
High Frequency Signal ◽  
3D Integrated Circuits ◽  
High Bandwidth ◽  
Silicon Vias

High frequency signal transmission through silicon substrates is critical for 3D heterogeneous integration. This paper presented fabrication, testing, and simulation of high-frequency interconnects based on through-silicon vias (TSVs) and coplanar waveguides (CPWs) for stacked 3D integrated circuits (3D ICs). Our simulation results showed that adding ground TSVs can improve signal transmission by 6× at 50GHz. We further investigated signal/ground TSV (1SXG) configurations for high-bandwidth signal transmission links. Scattering parameter measurements of fabricated 1SXG TSV structures for frequencies from 100MHz to 50GHz show low insertion loss (S21 less than −1dB up to 50GHz) and return loss (S11 lower than −15dB). These results indicate that these vertical interconnects exhibit good performance for high speed signal transmission. To understand the RF signal transmission in 3D interconnects, we used full wave electromagnetic simulation to investigate the electromagnetic field distribution associated with the ground TSV placement. We observed that the ground TSVs induced substantial overall field confinement, consistent with the experimental observation of improved signal transmission. Simulations also provided design guidance with respect to the substrate conductivity's impact on EM confinement and signal transmission.

Thermal-Electrical Co-Optimization of Block-Level Floorplanning in 3D Integrated Circuits

2009 ◽  
Author(s):  
Ankur Jain ◽  
Syed Alam ◽  
Scott Pozder ◽  
Robert E. Jones
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Integrated Circuit ◽  
Thermal Design ◽  
Maximum Temperature ◽  
Design Tools ◽  
Design Constraint ◽  
Trade Offs ◽  
Block Level ◽  
3D Integrated Circuits

While the stacking of multiple strata to produce 3D integrated circuits improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge due to the increased power density. There is a need for design tools to understand and optimize the trade-off between electrical and thermal design at the device and block level. This paper presents results from thermal-electrical co-optimization for block-level floorplanning in a multi-die 3D integrated circuit. A method for temperature computation based on linearity of the governing energy equation is presented. This method is shown to be faster and more accurate than previously used resistance-network based approaches and full-scale FEM simulations. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimize both the maximum temperature and the interconnect length. Results outline the various trade-offs between thermal and electrical considerations. It is shown that co-optimization of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Constraints placed by the 3D IC manufacturing process on design are outlined, showing that the cheapest manufacturing options may not result in optimal electrical and thermal design. In particular, the wafer-on-wafer bonding process requires the two die to be identical, which results in a severe design constraint, particularly on the thermal goal due to the overlap of high power density blocks. Results presented in this work highlight the need for thermal and electrical co-design in multistrata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D integrated circuits.

CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs

2019 ◽  
Vol 29 (11) ◽  
pp. 2050144
Author(s):  
Tianming Ni ◽  
Yue Shu ◽  
Hao Chang ◽  
Lin Lu ◽  
Guangzhen Dai ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Cost Effective ◽  
Bonding Process ◽  
High Yield ◽  
Repair Rate ◽  
3D Ics ◽  
Simulation Results ◽  
Silicon Vias

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring increases the faulty TSVs (FTSV), i.e., the TSV defects tend to be clustered which significantly reduces the yield of three-dimensional integrated circuits (3D-ICs). To resolve the clustered TSV faults, router-based and ring-based redundant TSV (RTSV) architecture were proposed. However, the repair rate is low and the hardware overhead is high. In this paper, we propose a novel cross-cellular based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has higher repair rate as well as more cost-effective overhead, compared with router-based and ring-based methods.

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

scholarly journals 2D Parity Product Code for TSV online fault correction and detection

2020 ◽  
Author(s):  
Khanh N. Dang ◽  
Akram Ben Ahmed ◽  
Abderazek Ben Abdallah ◽  
Michael Corad Meyer ◽  
Xuan-Tu Tran
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuits ◽  
Error Correction ◽  
Error Detection ◽  
Latin Square ◽  
Detection Rates ◽  
Product Code ◽  
3D Ics ◽  
High Detection ◽  
3D Integrated Circuits

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs).  However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults.  In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code.  In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

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