The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

Author(s):  
Horacio C. Nochetto ◽  
Nicholas R. Jankowski ◽  
Avram Bar-Cohen

The present work uses finite element thermal simulations of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) to evaluate the impact of device design parameters on the junction temperature. In particular the effects of substrate thickness, substrate thermal conductivity, GaN thickness, and GaN-to-substrate thermal boundary resistance (TBR) on device temperature rise are quantified. In all cases examined, the TBR was a dominant factor in overall device temperature rise. It is shown that a TBR increase can offset any benefits offered through a more conductive substrate and that there exists a substrate thickness independent of TBR which results in a minimum junction temperature. Additionally, the decrease of GaN thickness only provides a thermal benefit at small TBRs. For TBRs on the order of 10−4 cm2K/W or greater, decreasing the GaN thickness can actually increase the temperature as the heat from the highly localized source is not sufficiently spread out before crossing the GaN-substrate boundary. The tradeoff between GaN heat spreading, substrate heat spreading, and temperature rise across the TBR results in a GaN thickness with minimum total temperature rise. For the TBR values of 10−4 cm2K/W and 10−3 cm2K/W these GaN thicknesses are 0.8 μm and 9 μm respectively.

Author(s):  
Luke Yates ◽  
Thomas L. Bougher ◽  
Thomas Beechem ◽  
Baratunde A. Cola ◽  
Samuel Graham

The development of gallium nitride (GaN) on silicon (Si) substrates is a critical technology for potential low cost power electronics. These devices can accommodate faster switching speeds, hotter temperatures, and high voltages needed for power electronics applications. However, the lattice mismatch and difference in crystal structure between 111 Si and c-axis hexagonal GaN requires the use of buffer layers in order to grow device quality epitaxial layers. For lateral high electron mobility transistors, these interfacial layers act as a potential source of increased thermal boundary resistance (TBR) which impedes heat flow out of the GaN on Si devices. In addition, these interfacial layers impact the growth and residual stress in the GaN epitaxial layer which can play a role in device reliability. In this work we use optical methods to experimentally measure a relatively low TBR for GaN on Si with an intermediate buffer layer to be 3.8 ± 0.4 m2K/GW. The effective TBR of a material stack that encompasses GaN on Si with a superlattice (SL) buffer is also measured, and is found to be 107 ± 1 m2K/GW. In addition the residual state of strain in the GaN layer is measured for both samples, and is found to vary significantly between them. Thermal conductivity of a 0.8μm GaN layer on AlN buffer is determined to be 126 ± 25 W/m-K, while a 0.84 μm GaN layer with C-doping on a SL structure is determined to be 112 ± 29 W/m-K.


Author(s):  
Caleb A. Holloway ◽  
Avram Bar-Cohen

Three-dimensional finite-element modeling is used to determine the thermally optimum design of a GaN-on-SiC MMIC power amplifier, with a focus on the parametric influence of the thermal boundary resistance (TBR), epitaxial geometry, and dissipated linear power on the HEMT junction temperature rise. A commercial MMIC power amplifier is used to set the baseline geometry and dimensions. It is found that the frequently neglected Thermal Boundary Resistance (TBR), between the GaN and SiC, not only has a significant influence on the maximum junction temperature, but directly influences the thermally-optimal GaN thickness for the HEMT transistor. The thermally-optimal GaN thickness is a balance between spreading, vertical thermal resistance, and the magnitude of the TBR. As a consequence, it is seen the commonly used, submicron l GaN thicknesses approach optimality only when the TBR values are below 10 m2-K/GW. Additionally, it is observed that increasing the gate pitch and substrate thickness helps to diffuse the flow of heat within the substrate before it proceeds into the cooling solution, resulting in an overall decrease in thermal resistance. The numerical results are used to verify the accuracy of an available analytical solution for a surface heat source on an orthotropic multi-layer structure, albeit with assumed temperature-invariant properties, thus enabling use of this relation in scoping and preliminary design calculations.


Volume 4 ◽  
2004 ◽  
Author(s):  
Robert J. Stevens ◽  
Pamela M. Norris ◽  
Arthur W. Lichtenberger

Understanding thermal boundary resistance (TBR) is becoming increasingly important for the thermal management of micro and optoelectronic devices. The current understanding of room temperature TBR is often not adequate for the thermal design of tomorrow’s complex micro and nano devices. Theories have been developed to explain the resistance to energy transport by phonons across interfaces. The acoustic mismatch model (AMM) [1, 2], which has had success at explaining low temperature TBR, does not account for the high frequency phonons and imperfect interfaces of real devices at room temperature. The diffuse mismatch model (DMM) was developed to account for real surfaces with higher energy phonons [3, 4]. DMM assumes that all phonons incident on the interface from both sides are elastically scattered and then emitted to either side of the interface. The probability that a phonon is emitted to a particular side is proportional to the phonon density of states of the two interface materials. Inherent to the DMM is that the transport is independent of the interface structure itself and is only dependent on the properties of the two materials. Recent works have shown that the DMM does not adequately capture all the energy transport mechanisms at the interface [5, 6]. In particular, the DMM under-predicts transport across interfaces between non Debye-like materials, such at Pb and diamond, by approximately an order of magnitude. The DMM also tends to over-predict transport for interfaces made with materials of similar acoustic properties, Debye-like materials. There have been several explanations and models developed to explain the discrepancies between the mismatch models and experimental data. Some of these models are based on modification of the AMM and DMM [7–9]. Other works have utilized lattice-dynamical modeling to calculate phonon transmission coefficients and thermal boundary conductivities for abrupt and disordered interfaces [3, 6, 10–13]. Recent efforts to better understand room temperature TBR have utilized molecular dynamics simulations to account for more realistic anharmonic materials and inelastic scattering [14–18]. Models have also been developed to account for electron-phonon scattering and its effect on the thermal boundary conductance for interfaces with one metal side [19–22]. Although there have been numerous thermal boundary resistance theoretical developments since the introduction of the AMM, there still is not an unifying theory that has been well validated for high temperature solid-solid interfaces. Most of the models attempt to explain some of the experimental outliers, such as Pb/diamond and TiN/MgO interfaces [6, 23], but have not been fully tested for a range of experimental data. Part of the problem lies in the fact that very little reliable data is available, especially data that is systematically taken to validate a particular model. To this end, preliminary measurements of TBR are being made on a series of metal on non-metal substrate interfaces using a non-destructive optical technique, transient thermal reflectance (TTR) described in Stevens et al. [5]. Initial testing examines the impact of different substrate preparation and deposition conditions on TBR for Debye-like interfaces for which TBR should be small for clean and abrupt interfaces. Variables considered include sputter etching power and duration, electron beam source clean, and substrate temperature control. The impact of alloying and non-abrupt interfaces on the TBR is examined by fabricating interfaces of both Debye-like and non Debye-like interfaces followed by systematically measuring TBR and altering the interfaces by annealing the samples to increase the diffusion depths at the interfaces. Inelastic electron scattering at the interface has been proposed by Hubermann et al. and Sergeev to decrease TBR at interfaces [19–21]. Two sets of samples are prepared to examine the electron-phonon connection to improved thermal boundary conductance. The first consists of thin Pt and Ag films on Si and sapphire substrates. Pt and Ag electron-phonon coupling factors are 60 and 3.1×1016 W/m3K respectively. Both Pt and Ag have similar Debye temperatures, so electron scattering rates can be examined without much change in acoustic effects. The second electron scattering sample series consist of multiple interfaces fabricated with Ni, Ge, and Si to separate the phonon and electron portions of thermal transport. The experimental data is compared to several of the proposed theories.


Author(s):  
Anthony M. Pettes ◽  
Marc S. Hodes ◽  
Kenneth E. Goodson

Thermoelectric refrigerators (TEMs) offer several advantages over vapor-compression refrigerators. They are free of moving parts, acoustically silent, reliable and light-weight. Their low efficiency and peak heat flux capabilities have precluded their use in more widespread applications. Optimization of thermoelectric pellet geometry can help, but past work in this area has neglected the impact of thermal and electrical contact resistances. The present work extends a previous one-dimensional TEM model to account for a thermal boundary resistance and is appropriate for the common situation where an air-cooled heat sink is attached to a TEM. The model also accounts for the impact of electrical contact resistance at the TEM interconnects. The pellet geometry is optimized with the target of either maximum performance or efficiency for an arbitrary value of thermal boundary resistance for varying values of the temperature difference across the unit, the pellet Seebeck coefficient, and the contact resistances. The model predicts that when the thermal contact conductance is decreased by a factor of ten, the peak heat removal capability is reduced by at least 10 percent. Furthermore, when the interconnect electrical resistance rises above a factor of ten larger than the pellet electrical resistance, the maximum heat removal capability for a given pellet height is reduced by at least 20 percent and the maximum coefficient of performance at low Ku–∞u/(NK), values is reduced by at least 50 percent.


2006 ◽  
Vol 3 (4) ◽  
pp. 177-193 ◽  
Author(s):  
Andy Perkins ◽  
Krishna Tunga ◽  
Suresh Sitaraman

There is a need for a new Acceleration Factor (AF) that can relate Accelerated Thermal Cycle (ATC) fatigue life to Power Cycle (PC) fatigue life quickly and accurately in order to avoid over designing electronic packages for benign environments. An AF, such as the Norris-Landzberg AF, is only applicable when using it to predict fatigue life within the same environment, i.e. ATC to ATC or PC to PC. This work proposes an AF that takes into account the differences between ATC tests and PC tests for ceramic ball grid array (CBGA) packages by considering relevant design and environmental parameters. The new AF is based on relevant design parameters such as substrate size, substrate thermal conductivity, substrate thickness, coefficient of thermal (CTE) mismatch between the substrate and printed wiring board (PWB), PWB thickness, and environmental parameters such as temperature range (ΔT), frequency of cycles (f), and peak/junction temperature (Tj). Finite Element Models (FEM), experimental data, laser moiré interferometry, Design of Simulation (DOS), ANOVA, and regression analysis are used to develop the new AF. The new AF can be used to more accurately assess PC fatigue life from ATC tests so that expensive over-designing of electronic packages can be avoided for desktop/server/laptop applications.


2003 ◽  
Vol 764 ◽  
Author(s):  
Konstantin A. Filippov ◽  
Alexander A. Balandin

AbstractWe theoretically investigate the thermal boundary resistance and heat diffusion in AlGaN/GaN heterostructure field-effect transistors. Our calculations based on the diffuse mismatch model show that the thermal boundary resistance at the interface between GaN and SiC can strongly influence the temperature rise in the device channel.


Author(s):  
K.A. Filippov ◽  
A.A. Balandin

We have calculated the thermal boundary resistance at the GaN/SiC, GaN/sapphire and GaN/AlN interfaces in the diffuse mismatch approximation. The obtained values were then used to examine the effect of the thermal boundary resistance on heat diffusion in AlGaN/GaN heterostructure field-effect transistors. The results show that the thermal boundary resistance at the device layer interfaces can strongly influence the temperature rise in the device channel.


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