Fabrication and Reliability Assessment of Cu Pillar Micro-bumps with Printed Polymer Cores

2020 ◽  
Author(s):  
Xing QIU ◽  
Jeffery Lo ◽  
Yuanjie CHENG ◽  
Shi-Wei Ricky Lee ◽  
Yong Jhe TSENG ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Assessment ◽  
Temperature Cycling ◽  
Thermomechanical Stress ◽  
Joint Reliability ◽  
Cu Pillar ◽  
Bonding Technology ◽  
Temperature Cycling Test ◽  
Reliability Performance ◽  
Cycling Condition

Abstract Cu pillar micro-bumps with polymer cores have been demonstrated to effectively reduce thermomechanical stress and improve joint reliability. Fabricating polymer cores by a printing approach was proposed to overcome the limitations in conventional fabrication process. Cylindrical polymer cores with diameter of 20 µm and height of 30 µm were successfully printed. Surface metallization was subsequently applied on the printed polymer cores and Cu pillar micro-bumps with printed polymer cores with diameter of 35 µm and height of 35 µm were eventually achieved. To study the reliability performance of the interconnect joints made of Cu pillar micro-bumps with printed polymer cores, flip-chip bonding technology was successfully introduced and the interconnect joints between a designed BT substrate and a silicon chip were formed. The interconnect joints made of conventional Cu pillars with identical dimensions were prepared for comparison. The reliability performance of the joints was investigated under temperature cycling condition and drop condition, respectively. Printed polymer cores increased the characteristic life by 32% in a temperature cycling test (0°C-100°C), while the drop test showed that printed polymer cores increased the characteristic life by 4 times due to the extra compliance provided by the printed polymer cores. It can be concluded that Cu pillar micro-bumps with printed polymer cores can effectively reduce stress and improve joint reliability.

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

Influence of Glass Transition Temperature of Underfill on the Stress Behavior and Reliability of Microjoints Within a Chip Stacking Architecture

2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Jing-Yao Chang ◽  
Shin-Yi Huang ◽  
Chang-Chun Lee ◽  
Tung-Han Chuang ◽  
Tao-Chih Chang
Keyword(s):  
Glass Transition ◽  
Temperature Cycling ◽  
Stress And Strain ◽  
Analysis Model ◽  
Ansys Software ◽  
Depletion Zone ◽  
Reliability Characteristics ◽  
Temperature Cycling Test ◽  
Capillary Type ◽  
Reliability Performance

In this study, the reliability performance of two capillary-type underfill materials with different glass transition temperatures (Tg) and coefficients of thermal expansion (CTE) were assessed for a chip stacking architecture. The microbumps for integrating four chips on a Si interposer were with a pitch size of 20 μm and composed of 5 μm Cu/3 μm Ni/5 μm Sn2.5Ag solder cap. A thermocompressive bonder was used to interconnect the microbumps at 280 °C for 15 s, and the microgaps between the chips and the interposer were then, respectively, sealed by the mentioned underfill materials to form a chip stacking architecture. Then, the reliability characteristics of the test vehicles were evaluated following the preconditioning and temperature cycling test (TCT). Furthermore, a numerical analysis model was established by ansys software to study the stress and strain contours of the microjoints sealed by different underfill materials. It was found that the lifetime of microjoints was highly related to the Tg points of underfills, an interfacial fracture was observed within the microjoints sealed by a lower Tg underfill after temperature cycling because the tensile strength damaged the Sn depletion zone as heated.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

2018 ◽  
Vol 87 ◽  
pp. 97-105
Author(s):  
Melina Lofrano ◽  
Vladimir Cherman ◽  
Mario Gonzalez ◽  
Eric Beyne
Keyword(s):  
Flip Chip ◽  
Pillar Design ◽  
Thermomechanical Stress ◽  
Cu Pillar ◽  
Flip Chip Assembly

High Reliability Underfill for Flip-Chip Application

1996 ◽  
Vol 445 ◽  
Author(s):  
K. Sumita ◽  
K. Kumagae ◽  
K. Dobashi ◽  
T. Shiobara ◽  
M. Kuroda
Keyword(s):  
Ring Opening ◽  
Flip Chip ◽  
High Reliability ◽  
Void Formation ◽  
Ring Opening Polymerization ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Excellent Adhesion ◽  
Reliability Performance ◽  
Modified Epoxy

AbstractA new underfill was developed for a flip chip application with a large VLSI die. The new underfill is resistant to hydrolysis, exhibits a significantly lower moisture saturation level than widely used carboxylic anhydride cured underfills, demonstrates superb penetration capability between such a large die and an organic substrate without void formation, and delivers excellent adhesion characteristics and reliability performance during temperature cycling test and PCT (pressure cooker test).The new underfill utilizes amine catalyzed ring opening polymerization of epoxides, forms ether linkages during cure rather than ester linkages which anhydride cured underfills form, and strongly resists to hydrolysis. The underfill is less sensitive to moisture contamination and provides improved floor life as well as storage life in contrast to anhydride cured underfills as well. Unique low stress performance and penetration capability of the underfill are attributed to the use of proprietary silicone modified epoxy resin as well as highly loaded filler of optimized size, shape and size distribution in reference to the gap between a die and an organic substrate.An optimum cure schedule and a desirable viscosity range have also been identified for the new underfill to minimize filler segregation. Proper preheating of a die‐substrate has effectively reduced void formation while facilitating the removal of volatile from an organic substrate.

Physics Based Requirements for Qualification of BGA Components in Temperature Cycling

2015 ◽  
Author(s):  
Ru Han ◽  
Milena Vujosevic ◽  
Min Pei
Keyword(s):  
Deformation Process ◽  
Temperature Cycling ◽  
New Approach ◽  
Deformation And Failure ◽  
Joint Reliability ◽  
Rapid Changes ◽  
Temperature Cycling Test ◽  
Definition Of ◽  
The Impact ◽  
Package Materials

This paper discusses a new approach for definition of temperature cycling qualification requirement that accounts for the physics of the deformation process in use condition and in the accelerated temperature cycling test condition. The methodology is used to define solder joint reliability (SJR) requirement for Package on Package (PoP) components. Included in the study is the impact of adhesives on SJR requirements. The approach used is different from standards-based approaches that define the requirements in the way that is often independent of package materials and geometries. Physics based damage metrics and numerical modeling was used to comprehend design, technology, material, and temperature profile and provide an in-depth understanding of package deformation and failure mechanism. This, coupled with a developed fatigue law was then used to translate use conditions to test condition requirement. The study shows that accelerated test will not accelerate all PoP solder joints equally and that requirements for PoP to board interconnects will be different from requirements for top–to–bottom package interconnects. Similarly, for component with adhesives, when requirements are based on physics, they must be different than requirements for component without adhesive and those requirement should be a function of adhesive thermo-mechanical material properties. Given rapid changes in technology, explosion of new devices and new use conditions, manufacturers constantly make tradeoffs between performance, cost and reliability. The qualification process needs to be optimized to meet these increasing challenges and qualification based on knowledge of physics presented in this paper is designed to meet these challenges.

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