Stacking Yield Prediction of Package-on-Package Assembly Using Uncertainty Propagation Analysis—Part II: Implementation of Stochastic Model

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsiu-Ping Wei ◽  
Yu-Hsiang Yang ◽  
Bongtae Han

The stochastic model for yield loss prediction proposed in Part I is implemented for a package-on-package (PoP) assembly. The assembly consists of a stacked die thin flat ball grid array (TFBGA) as the top package and a flip chip ball grid array (fcBGA) as the bottom package. The top and bottom packages are connected through 216 solder joints of 0.5 mm pitch in two peripheral rows. The warpage values of the top and bottom package are calculated by finite element analysis (FEA), and the corresponding probability of density functions (PDFs) are obtained by the eigenvector dimension reduction (EDR) method. The solder ball heights of the top and bottom package and the corner pad joint heights are determined by surface evolver, and their PDFs are determined by the EDR method, too. Only 137 modeling runs are conducted to obtain all 549 PDFs in spite of the large number of input variables considered in the study (27 input variables). Finally, the noncontact open-induced staking yield loss of the PoP assembly is predicted from the PDFs.

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsiu-Ping Wei ◽  
Yu-Hsiang Yang ◽  
Bongtae Han

A comprehensive stochastic model is proposed to predict Package-on-Package (PoP) stacking yield loss. The model takes into account all pad locations at the stacking interface while considering the statistical variations of the warpages and the solder ball heights of both top and bottom packages. The goal is achieved by employing three statistical methods: (1) an advanced approximate integration-based method called eigenvector dimension reduction (EDR) method to conduct uncertainty propagation (UP) analyses, (2) the stress-strength interference (SSI) model to determine the noncontact probability at a single pad, and (3) the union of events considering the statistical dependence to calculate the final yield loss. In this first part, theoretical development of the proposed stochastic model is presented. Implementation of the proposed model is presented in a companion paper.


2013 ◽  
Vol 706-708 ◽  
pp. 1693-1696
Author(s):  
Hua Bin Zhao ◽  
De Jian Zhou

In the study of three-dimensional shape prediction of SMT solder joints, the software Surface Evolver has been widely applied as a quick and accurate effective tool for the prediction of solder joints shape. But the model it builds is not able to be directly imported into any finite element analysis software like ANSYS, and even after the import it still needs a lot of time to mend the import model. For this issue, to predict of the solder joints shape of ball grid array (BGA), the implement programs of three conversion methods of point-line-area method, axisymmetric method and infinitesimal method are given. By comparison, axisymmetric method and infinitesimal method are more suitable for the shape conversion of BGA solder joints.


2004 ◽  
Vol 126 (4) ◽  
pp. 560-564 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Jenq-Dah Wu

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001829-001856
Author(s):  
Tim Pham ◽  
Betty Yeung ◽  
Trent Uehling ◽  
Brett Wilkerson

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.


2013 ◽  
Vol 30 (1) ◽  
pp. 14-18 ◽  
Author(s):  
Yap Boon Kar ◽  
Noor Azrina Talik ◽  
Zaliman Sauli ◽  
Jean Siow Fei ◽  
Vithyacharan Retnasamy

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
S. B. Park ◽  
Rahul Joshi ◽  
Izhar Ahmed ◽  
Soonwan Chung

Experimental and numerical techniques are employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power cycling (PC) and accelerated thermal cycling (ATC). In PC, nonuniform temperature distribution and different coefficients of thermal expansion of each component make the package deform differently compared to the case of ATC. Traditionally, reliability assessment is conducted by ATC because ATC is believed to have a more severe thermal loading condition compared to PC, which is similar to the actual field condition. In this work, the comparative study of PC and ATC was conducted for the reliability of board level interconnects. The comparison was made using both ceramic and organic flip chip ball grid array packages. Moiré interferometry was adopted for the experimental stress analysis. In PC simulation, computational fluid dynamics analysis and finite element analysis are performed. The assembly deformations in numerical simulation are compared with those obtained by Moiré images. It is confirmed that for a certain organic package PC can be a more severe condition that causes solder interconnects to fail earlier than in ATC while the ceramic package fails earlier in ATC always.


2010 ◽  
Vol 148-149 ◽  
pp. 1108-1111 ◽  
Author(s):  
A. Jalar ◽  
Zainudin Kornain ◽  
Rozaidi Rasid ◽  
Saifollah Abdullah ◽  
Norinsan Kamil Othman

The possible source of die edge cracking for Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA) models were used to analyze the effect of underfill fillet geometry on interfacial stresses between die edge and the underfill fillet. The input parameters of FC-CBGA from industry was used for simulation and the properties of commercial underfill were extracted by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). Die stress distribution for different fillet height were generated to depict variation of stress due thermal loading. The variation of tensile stress due different fillet height and width were discussed for parameters optimization.


2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.


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