Flip Chip Fine Pitch PBGA Yield Study

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001829-001856
Author(s):  
Tim Pham ◽  
Betty Yeung ◽  
Trent Uehling ◽  
Brett Wilkerson
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Simulations ◽  
Flip Chip ◽  
Yield Loss ◽  
Combined Effect ◽  
Electrical Performance ◽  
Design Parameters ◽  
Surface Evolver ◽  
Solidification Temperature ◽  
Fine Pitch

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.

Stacking Yield Prediction of Package-on-Package Assembly Using Uncertainty Propagation Analysis—Part II: Implementation of Stochastic Model

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsiu-Ping Wei ◽  
Yu-Hsiang Yang ◽  
Bongtae Han
Keyword(s):  
Stochastic Model ◽  
Flip Chip ◽  
Yield Loss ◽  
Uncertainty Propagation ◽  
Ball Grid Array ◽  
Surface Evolver ◽  
Element Analysis ◽  
Loss Prediction ◽  
Eigenvector Dimension Reduction ◽  
Input Variables

The stochastic model for yield loss prediction proposed in Part I is implemented for a package-on-package (PoP) assembly. The assembly consists of a stacked die thin flat ball grid array (TFBGA) as the top package and a flip chip ball grid array (fcBGA) as the bottom package. The top and bottom packages are connected through 216 solder joints of 0.5 mm pitch in two peripheral rows. The warpage values of the top and bottom package are calculated by finite element analysis (FEA), and the corresponding probability of density functions (PDFs) are obtained by the eigenvector dimension reduction (EDR) method. The solder ball heights of the top and bottom package and the corner pad joint heights are determined by surface evolver, and their PDFs are determined by the EDR method, too. Only 137 modeling runs are conducted to obtain all 549 PDFs in spite of the large number of input variables considered in the study (27 input variables). Finally, the noncontact open-induced staking yield loss of the PoP assembly is predicted from the PDFs.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000441-000454
Author(s):  
Siddharth Bhopte ◽  
Jesse Galloway ◽  
Kyung-Rok Park ◽  
Hyun-Jin Park ◽  
Jeong-Han Choi ◽  
...  
Keyword(s):  
Flip Chip ◽  
Computational Study ◽  
Heating Temperature ◽  
Form Factors ◽  
Temperature Gradients ◽  
Electrical Performance ◽  
Large Temperature ◽  
Compression Load ◽  
Chip Technology ◽  
Fine Pitch

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (<60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Low-voltage EDS of magnesium ferrite Dendrites in a FEG-SEM

1996 ◽  
Vol 54 ◽  
pp. 478-479
Author(s):  
Matthew T. Johnson ◽  
Ian M. Anderson ◽  
Jim Bentley ◽  
C. Barry Carter
Keyword(s):  
Monte Carlo ◽  
Quantitative Analysis ◽  
Monte Carlo Simulations ◽  
Cross Section ◽  
Spatial Resolution ◽  
Low Voltage ◽  
Magnesium Ferrite ◽  
X Ray ◽  
Interaction Volume ◽  
Ferrite Spinel

Energy-dispersive X-ray spectrometry (EDS) performed at low (≤ 5 kV) accelerating voltages in the SEM has the potential for providing quantitative microanalytical information with a spatial resolution of ∼100 nm. In the present work, EDS analyses were performed on magnesium ferrite spinel [(MgxFe1−x)Fe2O4] dendrites embedded in a MgO matrix, as shown in Fig. 1. spatial resolution of X-ray microanalysis at conventional accelerating voltages is insufficient for the quantitative analysis of these dendrites, which have widths of the order of a few hundred nanometers, without deconvolution of contributions from the MgO matrix. However, Monte Carlo simulations indicate that the interaction volume for MgFe2O4 is ∼150 nm at 3 kV accelerating voltage and therefore sufficient to analyze the dendrites without matrix contributions.Single-crystal {001}-oriented MgO was reacted with hematite (Fe2O3) powder for 6 h at 1450°C in air and furnace cooled. The specimen was then cleaved to expose a clean cross-section suitable for microanalysis.

MONTE CARLO SIMULATIONS OF ELECTRON DRIFT VELOCITIES IN THE NOBLE GASES AND THEIR MIXTURES

1979 ◽  
Vol 40 (C7) ◽  
pp. C7-63-C7-64
Author(s):  
A. J. Davies ◽  
J. Dutton ◽  
C. J. Evans ◽  
A. Goodings ◽  
P.K. Stewart
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Simulations ◽  
Noble Gases ◽  
Electron Drift
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