Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Saketh Mahalingam ◽  
Ananth Prabhakumar ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Experimental Data ◽  
Thermal Shock ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Thermomechanical Fatigue ◽  
Interfacial Delamination ◽  
Shock Testing ◽  
Solder Bumps ◽  
Theoretical Predictions ◽  
Flip Chip Assembly

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Reliability Evaluation of Underfill Encapsulated Pb-Free Flip Chip Package under Thermal Shock Test

2007 ◽  
Vol 544-545 ◽  
pp. 621-624
Author(s):  
Dae Gon Kim ◽  
Jong Woong Kim ◽  
Sang Su Ha ◽  
Ja Myeong Koo ◽  
Bo In Noh ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Flip Chip ◽  
Solder Bump ◽  
Initial Reaction ◽  
Thermal Shock Test ◽  
Shock Testing ◽  
Thermally Activated ◽  
Solder Fatigue ◽  
Two Phases ◽  
Electroless Ni

Thermo-mechanical reliability of the solder bumped flip chip packages having underfill encapsulant was evaluated with thermal shock testing. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 IMC layer, while the two phases which were (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 were formed between the solder and electroless Ni-P layer of the package side. A crack was formed at the upper edge region of solder bump, and propagated through the solder region. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally activated solder fatigue failure. After thermal shocks of 2000 cycles, one more crack which was not observed in the case of non-underfill encapsulated flip chip was observed at the left side of interface between solder bump and substrate. The addition of this crack formation should be due to the underfill encapsulation between the Si chip and substrate.

A Model for Deformation of Solder Bumps From Ramp Loading

1996 ◽  
Vol 118 (1) ◽  
pp. 37-40
Author(s):  
Lewis S. Goldmann
Keyword(s):  
Experimental Data ◽  
Simple Model ◽  
Solder Joint ◽  
Flip Chip ◽  
Simple Algorithm ◽  
Ball Grid Array ◽  
Joint Reliability ◽  
Subsequent Processing ◽  
Solder Bumps

A simple model is presented to predict the mechanical squashing or stretching of an axisymmetric solder joint when subjected to a ramp loading. This is a situation which can frequently arise, accidentally or by design, in the processing of flip chip solder bumps, or in surface mounted Ball Grid Array modules. Excessive squashing can have ramifications for subsequent processing or for joint reliability. The proposed method, while involving an extremely simple algorithm, has been found to agree well with experimental data, and is very general in its applicability.

Flip-chip assembly and reliability using gold/tin solder bumps

2004 ◽  
Author(s):  
Hermann Oppermann ◽  
Matthias Hutter ◽  
Matthias Klein ◽  
Herbert Reichl
Keyword(s):  
Flip Chip ◽  
Solder Bumps ◽  
Flip Chip Assembly

Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps

2005 ◽  
Vol 863 ◽  
Author(s):  
Hermann Oppermann ◽  
Matthias Hutter ◽  
Matthias Klein ◽  
Gunter Engelmann ◽  
Michael Toepper ◽  
...  
Keyword(s):  
Substrate Temperature ◽  
Flip Chip ◽  
Failure Modes ◽  
Compound Semiconductors ◽  
Temperature Cycling ◽  
Reliability Test ◽  
Test Results ◽  
Solder Bumps ◽  
Flip Chip Assembly ◽  
Gold Metallization

AbstractAu/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

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