Flip-chip assembly and reliability using gold/tin solder bumps

2004 ◽  
Author(s):  
Hermann Oppermann ◽  
Matthias Hutter ◽  
Matthias Klein ◽  
Herbert Reichl
Keyword(s):  
Flip Chip ◽  
Solder Bumps ◽  
Flip Chip Assembly

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps

2005 ◽  
Vol 863 ◽  
Author(s):  
Hermann Oppermann ◽  
Matthias Hutter ◽  
Matthias Klein ◽  
Gunter Engelmann ◽  
Michael Toepper ◽  
...  
Keyword(s):  
Substrate Temperature ◽  
Flip Chip ◽  
Failure Modes ◽  
Compound Semiconductors ◽  
Temperature Cycling ◽  
Reliability Test ◽  
Test Results ◽  
Solder Bumps ◽  
Flip Chip Assembly ◽  
Gold Metallization

AbstractAu/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Saketh Mahalingam ◽  
Ananth Prabhakumar ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Experimental Data ◽  
Thermal Shock ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Thermomechanical Fatigue ◽  
Interfacial Delamination ◽  
Shock Testing ◽  
Solder Bumps ◽  
Theoretical Predictions ◽  
Flip Chip Assembly

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.

Reliable Low-Cost Flip Chip Interconnections

2001 ◽  
Author(s):  
Z. W. Zhong
Keyword(s):  
Mass Production ◽  
Flip Chip ◽  
Material Selection ◽  
Low Cost ◽  
Assembly Process ◽  
Eutectic Solder ◽  
Solder Bumps ◽  
Key Issues ◽  
Flip Chip Assembly ◽  
Reliability Performance

Abstract A few reliable low-cost flip chip assembly processes using gold bumps with NCA, ACF or ACP that involved daily mass production activities in the industry are reported in this paper. Some key issues of material selection and assembly for reliable low-cost flip chip interconnections are discussed. This paper also discusses reliable low-cost processes of flip chip on FR-4 using eutectic solder bumps with possible fewer process steps compared to the full assembly process. Some interesting results with respect to the reliability performance of the processes have been obtained.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps
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