Reliability Prediction of Area Array Solder Joints

2003 ◽  
Vol 125 (4) ◽  
pp. 562-568 ◽  
Author(s):  
Rainer Dudek ◽  
Ralf Do¨ring ◽  
Bernd Michel
Keyword(s):  
Geometric Modeling ◽  
Flip Chip ◽  
Failure Criteria ◽  
Temperature Fields ◽  
The Finite Element Method ◽  
Chip Technology ◽  
Array Technology ◽  
Chip Scale Package ◽  
Solder Balls

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Ultra-Thin and High-Density Packaging Using Both Sides Flip Chip Technology

2003 ◽  
Author(s):  
Kazuto Nishida ◽  
Kazumichi Shimizu ◽  
Michiro Yoshino ◽  
Hideo Koguchi ◽  
Nipon Taweejun
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
High Capacity ◽  
High Density ◽  
Thickness Direction ◽  
The Finite Element Method ◽  
Memory Card ◽  
Chip Technology ◽  
Chip Size ◽  
High Density Packaging

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).

Characterization of the ternary phase at the Sn/Ni–V joint

2008 ◽  
Vol 23 (10) ◽  
pp. 2743-2748 ◽  
Author(s):  
Chih-chi Chen ◽  
Sinn-wen Chen ◽  
Chih-horng Chang
Keyword(s):  
Activation Energy ◽  
Amorphous Phase ◽  
Ternary Phase ◽  
Flip Chip ◽  
Interfacial Reactions ◽  
Fast Diffusion ◽  
Chip Technology ◽  
Primary Element ◽  
T Phase

Ni–7 wt% V diffusion barrier is commonly used in flip chip technology, and Sn is the primary element of all commercial electronic solders. Different from the interfacial reactions in the Sn/Ni couples, a ternary T phase is formed in the Sn/Ni–7 wt% V couples reacted at temperatures lower than 350 °C. The T phase is a mixture of an amorphous phase and the Ni3Sn4 phase with grains about 50 nm in size. The amorphous phase is composed mainly of Sn and V atoms, and it is formed due to the fast diffusion of Sn and relative immobility of V. Activation energy of the T phase formation is 16.5 kJ/mol, which is approximately 50% of that of the Ni3Sn4 phase determined from the Sn/Ni interfacial reactions. The T phase is no longer formed and the reaction product is the Ni3Sn4 phase in the Sn/Ni–7 wt% V couples reacted at temperatures higher than 350 °C.

scholarly journals Simulation Research on Sparse Reconstruction for Defect Signals of Flip Chip Based on High-Frequency Ultrasound

2020 ◽  
Vol 10 (4) ◽  
pp. 1292
Author(s):  
Xiaonan Yu ◽  
Hairun Huang ◽  
Wanlong Xie ◽  
Jiefei Gu ◽  
Ke Li ◽  
...  
Keyword(s):  
High Frequency ◽  
Flip Chip ◽  
Acoustic Energy ◽  
Acoustic Microscopy ◽  
Propagation Path ◽  
Sparse Reconstruction ◽  
High Frequency Ultrasound ◽  
Microscopy Imaging ◽  
Chip Technology ◽  
Solder Balls

Flip chip technology has been widely used in various fields. As the density of the solder balls in flip chip technology is increasing, the pitch among solder balls is narrowing, and the size effect is more significant. Therefore, the micro defects of the solder balls are more difficult to detect. In order to ensure the reliability of the flip chip, it is very important to detect and evaluate the micro defects of solder balls. High-frequency ultrasonic testing technology is an effective micro-defect detection method. In this paper, the interaction mechanism between high-frequency ultrasonic pulse and micro defects is analyzed by finite element simulation. A transient simulation model for the whole process of ultrasonic scanning of micro defects is established to simulate scanning in acoustic microscopy imaging. The acoustic propagation path map is obtained for analyzing acoustic energy transmission during detection, and the edge blurring effect in micro-defect imaging detection is clarified. The processing method of the time-domain signal and cross-section image signal of micro defects based on sparse reconstruction is studied, which can effectively improve the accuracy of detection and the signal-to-noise ratio.

3D Wire Bondless Integration: The Future of Silicon Carbide (SiC) Packaging

2017 ◽  
Author(s):  
Sayan Seal ◽  
Andrea K. Wallace ◽  
John E. Zumbro ◽  
H. Alan Mantooth
Keyword(s):  
Electromagnetic Interference ◽  
Flip Chip ◽  
Wide Bandgap ◽  
Switching Losses ◽  
Wire Bonds ◽  
Electrical Interconnection ◽  
Power Modules ◽  
Chip Scale Package ◽  
Solder Balls ◽  
High Temperature Operation

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Evaluation of electromigration in flip-chip solder joints

2011 ◽  
Vol 2011 (1) ◽  
pp. 000979-000984 ◽  
Author(s):  
Hyun-Kyu Lee ◽  
Yong-Chul Chu ◽  
Myung-Ho Chun ◽  
Sang-Ho Jeon ◽  
Jung-Ug Kwak ◽  
...  
Keyword(s):  
Electric Current ◽  
Flip Chip ◽  
Solder Joints ◽  
Cathode Side ◽  
Time To Failure ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Balls ◽  
Initial Resistance ◽  
Reliability Issue

The flip-chip solder joint has become one of the most important technologies of high-density packaging in the microelectronics industry. But, electromigration has become a critical reliability issue in flip-chip technology. Because the dimensions of solder joints are expected to decrease and current density is expected to increase. This study is about electromigration of flip-chip solder joints, we evaluated many kinds of solder balls such as SnAgCu, SnCu and so on in flip chip package. The lifetime against electromigration was defined the fail from the value of resistance with electric current reaches 1.5 times of that of initial resistance with electric current for. In solder bumps with electric current, since the atoms composed of the solder bump and UBM move in the direction of electron flows, the IMC was accumulated on the anode side. Meanwhile, the IMC disappeared in the cathode side, and the voids were formed. In the solder bumps without electric current, the IMC gradually grew on both sides. SnAgCu had better lifetime than SnCu, and different time-to-failure caused by different crystallographic orientation of Sn. And various dopants in SnCu had a different EM lifetime each other.

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