Small Delay Fault Model for Intra-Gate Resistive Open Defects

2009 27th IEEE VLSI Test Symposium ◽

10.1109/vts.2009.25 ◽

2009 ◽

Cited By ~ 7

Author(s):

Masayuki Arai ◽

Akifumi Suto ◽

Kazuhiko Iwasaki ◽

Katsuyuki Nakano ◽

Michihiro Shintani ◽

...

Keyword(s):

Fault Model ◽

Delay Fault ◽

Small Delay ◽

Open Defects ◽

Resistive Open Defects

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A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

2008 13th European Test Symposium ◽

10.1109/ets.2008.19 ◽

2008 ◽

Cited By ~ 32

Author(s):

Alejandro Czutro ◽

Nicolas Houarche ◽

Piet Engelke ◽

Ilia Polian ◽

Mariane Comte ◽

...

Keyword(s):

Delay Faults ◽

Small Delay ◽

Open Defects ◽

Resistive Open Defects

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A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741773 ◽

2019 ◽

Author(s):

Chao-Jun Shang ◽

Cheng-Hung Wu ◽

Kuen-Jong Lee ◽

Yu-Hsiang Chen

Keyword(s):

Test Generation ◽

Fault Model ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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Path Delay Fault Model

High Quality Test Pattern Generation and Boolean Satisfiability ◽

10.1007/978-1-4419-9976-4_8 ◽

2012 ◽

pp. 155-180

Author(s):

Stephan Eggersglüß ◽

Rolf Drechsler

Keyword(s):

Fault Model ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Testing for resistive open defects in FPGAs

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. ◽

10.1109/fpt.2002.1188704 ◽

2003 ◽

Cited By ~ 7

Author(s):

M.B. Tahoori

Keyword(s):

Open Defects ◽

Resistive Open Defects

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Improving small-delay fault coverage for on-chip delay measurement

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2012.6378223 ◽

2012 ◽

Cited By ~ 4

Author(s):

Wenpo Zhang ◽

Kazuteru Namba ◽

Hideo Ito

Keyword(s):

Fault Coverage ◽

Delay Fault ◽

Delay Measurement ◽

Small Delay ◽

On Chip

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Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model

Second IEEE International Workshop on Electronic Design, Test and Applications ◽

10.1109/delta.2004.10080 ◽

2005 ◽

Author(s):

Shyue-Kung Lu ◽

Mau-Jung Lu

Keyword(s):

Fault Model ◽

Fir Filters ◽

Delay Fault

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GPU-Accelerated Small Delay Fault Simulation

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0077 ◽

2015 ◽

Cited By ~ 14

Author(s):

Eric Schneider ◽

Stefan Holst ◽

Michael A. Kochte ◽

Xiaoqing Wen ◽

Hans-Joachim Wunderlich

Keyword(s):

Fault Simulation ◽

Delay Fault ◽

Small Delay

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Process-variability aware delay fault testing of ΔV/sub T/ and weak-open defects

The Eighth IEEE European Test Workshop, 2003. Proceedings. ◽

10.1109/etw.2003.1231673 ◽

2004 ◽

Cited By ~ 2

Author(s):

D. Arumi-Delgado ◽

R. Rodriguez-Montanes ◽

J.P. de Gyvez ◽

G. Gronthoud

Keyword(s):

Fault Testing ◽

Process Variability ◽

Delay Fault ◽

Delay Fault Testing ◽

Open Defects

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A delay fault model for at-speed fault simulation and test generation

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1145/1233501.1233521 ◽

2006 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Fault Model ◽

Delay Fault

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Diagnosis of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW) ◽

10.1109/iirw.2014.7049521 ◽

2014 ◽

Cited By ~ 3

Author(s):

Woongrae Kim ◽

Chang-Chih Chen ◽

Linda Milor

Keyword(s):

Open Defects ◽

Resistive Open Defects

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