IP Session 7C: Design for Yield and Manufacturability

Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)

2019 IEEE 37th VLSI Test Symposium (VTS) ◽

10.1109/vts.2019.8758652 ◽

2019 ◽

Author(s):

Soowang Park ◽

Sandeep K. Gupta

Keyword(s):

Cache Design ◽

Design For Yield

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Logic characterization vehicle design for yield learning

2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) ◽

10.1109/asmc.2016.7491080 ◽

2016 ◽

Author(s):

Ben Niewenhuis ◽

Zeye Dexter Liu ◽

Soumya Mittal ◽

R. D. Shawn Blanton

Keyword(s):

Vehicle Design ◽

Yield Learning ◽

Design For Yield

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A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Design-Process-Technology Co-optimization for Manufacturability XIII ◽

10.1117/12.2514896 ◽

2019 ◽

Author(s):

Jaehwan Kim ◽

Sangah Lee ◽

Byungchul Shin ◽

Junsu Jeon ◽

Jin Kim ◽

...

Keyword(s):

Technology Node ◽

Novel Design ◽

Design For Yield

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On Optimal Latin Hypercube Design for Yield Analysis of Analog Circuits

2015 Austrian Workshop on Microelectronics ◽

10.1109/austrochip.2015.14 ◽

2015 ◽

Cited By ~ 2

Author(s):

Hiwa Mahmoudi ◽

Horst Zimmermann

Keyword(s):

Analog Circuits ◽

Latin Hypercube Design ◽

Latin Hypercube ◽

Yield Analysis ◽

Optimal Latin Hypercube Design ◽

Design For Yield

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Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.73 ◽

2005 ◽

Cited By ~ 3

Author(s):

S. Mukhopadhyay ◽

A. Raychowdhury ◽

H. Mahmoodi ◽

K. Roy

Keyword(s):

Leakage Current ◽

Yield Enhancement ◽

Sense Amplifier ◽

Nano Scale ◽

Amplifier Design ◽

Design For Yield

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DFY/DFM - design for yield and manufacturability (industrial tutorial)

Proceedings Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2004.1268807 ◽

2004 ◽

Author(s):

A. Ripp ◽

R. Sommer ◽

E. Hennig ◽

M. Pronath

Keyword(s):

Design For Yield

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Pre-Tapeout Design for Yield Application: Design based Diffing, Pattern Analytics and Risk Scoring

2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) ◽

10.1109/edtm.2018.8421477 ◽

2018 ◽

Cited By ~ 1

Author(s):

Rami Salem ◽

Vic Vadi ◽

Angelo Pinto ◽

Piyush Pathak ◽

Ya-Chieh Lai ◽

...

Keyword(s):

Risk Scoring ◽

Application Design ◽

Design For Yield

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Design for manufacturing? design for yield!!!

International Symposium on Signals Circuits and Systems Proceedings SCS 2003 (Cat No 03EX720) ISQED-04 ◽

10.1109/isqed.2004.1283643 ◽

2005 ◽

Cited By ~ 1

Author(s):

M. Levitt

Keyword(s):

Design For Manufacturing ◽

Manufacturing Design ◽

Design For Yield

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Design for Yield and Reliability is MORE Important Than DFT

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805877 ◽

2005 ◽

Author(s):

D.M.H. Walker

Keyword(s):

Design For Yield

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Simultaneous layout, process, and model optimization within an integrated design-for-yield environment

10.1117/12.681806 ◽

2006 ◽

Author(s):

Dmitri Lapanik ◽

Lynn Cai ◽

Chung-Shin Kang ◽

Bob Naber ◽

Jason Sweis ◽

...

Keyword(s):

Integrated Design ◽

Model Optimization ◽

Design For Yield

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