Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

2005 ◽  
Author(s):  
S. Mukhopadhyay ◽  
A. Raychowdhury ◽  
H. Mahmoodi ◽  
K. Roy
Keyword(s):  
Leakage Current ◽  
Yield Enhancement ◽  
Sense Amplifier ◽  
Nano Scale ◽  
Amplifier Design ◽  
Design For Yield

Cell Charge Loss by Formation of Inversion Channel in DRAM

2020 ◽  
Author(s):  
Hoonchang Yang ◽  
Keunchul Ryu ◽  
Dongin Seo ◽  
Kyoungrak Cho ◽  
Junsik Park ◽  
...  
Keyword(s):  
Leakage Current ◽  
Study Data ◽  
Electron Loss ◽  
Voltage Level ◽  
Sense Amplifier ◽  
Read Operation ◽  
Related Cell ◽  
Inversion Channel ◽  
Charge Loss ◽  
Cell Capacitance

Abstract As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER

2011 ◽  
Vol 20 (08) ◽  
pp. 1659-1675 ◽  
Author(s):  
ASHWANI K. RANA ◽  
NAROTTAM CHAND ◽  
VINOD KAPOOR
Keyword(s):  
Leakage Current ◽  
Scale Effects ◽  
Current Model ◽  
Tunneling Current ◽  
Oxide Semiconductor ◽  
Experimental Result ◽  
Gate Leakage ◽  
Gate Current ◽  
Nano Scale ◽  
Gate Tunneling

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

scholarly journals Low Power Sub Threshold QDI Kogge Stone Adder using Sense Amplifier Lector based Half Buffer Cell Templates

2019 ◽  
Vol 8 (11S2) ◽  
pp. 173-179
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
High Performance ◽  
Slew Rate ◽  
Large Area ◽  
Signaling Protocol ◽  
Sense Amplifier ◽  
Area Overhead ◽  
Circuit Structure ◽  
Time Fall

Nowadays power consumption has the highest priority in designing high-performance electronics systems. The main purpose of this paper is to present a 16-bitKogge-Stone Adder where the low control operation is attained by the decrease of exchanging action. In this paper, we propose a method called Sense amplifier Lector based Half-Buffer (SALHB) by exemplifying Sense Amplifier Half Buffer (SAHB) with LECTOR algorithm to lessen leakage current in circuit structure. A 16-piece Kogge Stone Adder (KSA) is structured and actualized utilizing an asynchronous Quasi-Delay-Insensitive cell configuration approach known as the SALHB algorithm. Generally, SAHB is an asynchronous QDI configuration approach which applies 4-phase signaling protocol and sub-edge operation to obtain low control dissipation and rapid of operation. Additionally, LECTOR algorithm is applied to SAHB configuration approach through which leakage current can be decreased further to a great degree. A portion of the asynchronous QDI cell templates are Pre-charged Half-buffer(PCHB) and Autonomous signal validity Half-buffer(ASVHB), as both the templates, use completion detector circuits which lead to high power dissipation and large area overhead. SAHB design surpasses these drawbacks. But, SAHB has more leakage current. Hence, SALHB method was proposed to overcome the problem of high leakage current. In this paper, the performance of KSA is analyzed in terms of power, delay, energy, rise time, fall time, settle time, duty cyle, throughput and slew rate.

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