International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)
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167

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Published By Int. Test. Conference

0780357531

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High-level ATPG for Early Power Analysis

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805853 ◽

2005 ◽

Author(s):

W. Roethig

Keyword(s):

Power Analysis ◽

High Level

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High time for high level ATPG

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805848 ◽

2005 ◽

Author(s):

Wu-Tung Cheng

Keyword(s):

High Time ◽

High Level

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Thin Gate Oxide Reliability

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805855 ◽

2005 ◽

Author(s):

J.L. Roehr

Keyword(s):

Gate Oxide ◽

Oxide Reliability ◽

Thin Gate Oxide

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Scan Insertion at the Behavioral Level

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805858 ◽

2005 ◽

Author(s):

C. Aktouf

Keyword(s):

Behavioral Level

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Analog Fault Simulation: Key to Product Quality, or a Foot in the Door

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805791 ◽

2005 ◽

Cited By ~ 2

Author(s):

C. Force

Keyword(s):

Product Quality ◽

Fault Simulation ◽

Analog Fault Simulation

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Is Analog Fault Simulation a Key to Product Quality? Practical Considerations

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805789 ◽

2005 ◽

Cited By ~ 1

Author(s):

B. Kaminska

Keyword(s):

Product Quality ◽

Fault Simulation ◽

Analog Fault Simulation

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Analog Fault Simulation: Need it? No. It is already done

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805790 ◽

2005 ◽

Cited By ~ 1

Author(s):

E.R. Atwood

Keyword(s):

Fault Simulation ◽

Analog Fault Simulation

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Design for Yield and Reliability is MORE Important Than DFT

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805877 ◽

2005 ◽

Author(s):

D.M.H. Walker

Keyword(s):

Design For Yield

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It Makes Sense to Combine DFT and DFR/DFY

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805874 ◽

2005 ◽

Author(s):

R.C. Aitken

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Position Statement: Increasing Test Coverage in a VLSI Design Course

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805864 ◽

2005 ◽

Author(s):

J.A. Abraham

Keyword(s):

Vlsi Design ◽

Position Statement ◽

Test Coverage

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International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Int. Test. Conference

High-level ATPG for Early Power Analysis

High time for high level ATPG

Thin Gate Oxide Reliability

Scan Insertion at the Behavioral Level

Analog Fault Simulation: Key to Product Quality, or a Foot in the Door

Is Analog Fault Simulation a Key to Product Quality? Practical Considerations

Analog Fault Simulation: Need it? No. It is already done

Design for Yield and Reliability is MORE Important Than DFT

It Makes Sense to Combine DFT and DFR/DFY

Position Statement: Increasing Test Coverage in a VLSI Design Course

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)
Latest Publications