Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 μm pitch isolation and beyond

2002 ◽  
Author(s):  
K. Horita ◽  
T. Kuroi ◽  
Y. Itoh ◽  
K. Shiozawa ◽  
K. Eikyu ◽  
...  
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Channel Effects

Enhanced radiation-induced narrow channel effects in 0.13-${\boldsymbol{\mu }}{\rm{m}}$ PDSOI nMOSFETs with shallow trench isolation

2018 ◽  
Vol 27 (2) ◽  
pp. 028501 ◽  
Author(s):  
Meng-Ying Zhang ◽  
Zhi-Yuan Hu ◽  
Da-Wei Bi ◽  
Li-Hua Dai ◽  
Zheng-Xuan Zhang
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Channel Effects ◽  
Radiation Induced

Shallow trench isolation-related narrow channel effect on the kink behaviour of 40nm PD SOI NMOS device

2010 ◽  
Vol 54 (5) ◽  
pp. 609-611
Author(s):  
H.J. Hung ◽  
J.B. Kuo ◽  
D. Chen ◽  
C.T. Tsai ◽  
C.S. Yeh
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Channel Effect ◽  
Trench Isolation

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

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