Improving the quality of sub-1.5-nm-thick oxynitride gate dielectric for FETs with narrow channel and shallow-trench isolation using radical oxygen and nitrogen

2002 ◽  
Vol 49 (10) ◽  
pp. 1736-1741 ◽  
Author(s):  
M. Togo ◽  
K. Watanabe ◽  
M. Terai ◽  
T. Yamamoto ◽  
T. Fukai ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Shallow trench isolation-related narrow channel effect on the kink behaviour of 40nm PD SOI NMOS device

2010 ◽  
Vol 54 (5) ◽  
pp. 609-611
Author(s):  
H.J. Hung ◽  
J.B. Kuo ◽  
D. Chen ◽  
C.T. Tsai ◽  
C.S. Yeh
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Channel Effect ◽  
Trench Isolation

Enhanced radiation-induced narrow channel effects in 0.13-${\boldsymbol{\mu }}{\rm{m}}$ PDSOI nMOSFETs with shallow trench isolation

2018 ◽  
Vol 27 (2) ◽  
pp. 028501 ◽  
Author(s):  
Meng-Ying Zhang ◽  
Zhi-Yuan Hu ◽  
Da-Wei Bi ◽  
Li-Hua Dai ◽  
Zheng-Xuan Zhang
Keyword(s):  
Narrow Channel ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Channel Effects ◽  
Radiation Induced

Improvement in Gate Dielectric Quality of Ultra Thin a: SiN:H MNS Capacitor by Hydrogen Etching of the Substrate

2002 ◽  
Vol 716 ◽  
Author(s):  
Parag C. Waghmare ◽  
Samadhan B. Patil ◽  
Rajiv O. Dusane ◽  
V.Ramgopal Rao
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectric ◽  
Substrate Surface ◽  
Scaling Limit ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Poor Performance ◽  
State Density ◽  
Direct Tunneling Current

AbstractTo extend the scaling limit of thermal SiO2, in the ultra thin regime when the direct tunneling current becomes significant, members of our group embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. Silicon nitride can be deposited using several CVD methods and its properties significantly depend on the method of deposition. Although these CVD methods can give good physical properties, the electrical properties of devices made with CVD silicon nitride show very poor performance related to very poor interface, poor stability, presence of large quantity of bulk traps and high gate leakage current. We have employed the rather newly developed Hot Wire Chemical Vapor Deposition (HWCVD) technique to develop the a:SiN:H material. From the results of large number of optimization experiments we propose the atomic hydrogen of the substrate surface prior to deposition to improve the quality of gate dielectric. Our preliminary results of these efforts show a five times improvement in the fixed charges and interface state density.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

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