Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

2018 IEEE International Test Conference (ITC) ◽

10.1109/test.2018.8624725 ◽

2018 ◽

Cited By ~ 9

Author(s):

S. M. Nair ◽

R. Bishnoi ◽

M. B. Tahoori ◽

G. Tshagharyan ◽

H. Grigoryan ◽

...

Keyword(s):

Fault Modeling ◽

Defect Injection ◽

Test Algorithm ◽

Algorithm Generation

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Simulation-based test algorithm generation and port scheduling for multi-port memories

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1145/378239.378491 ◽

2001 ◽

Cited By ~ 9

Author(s):

Chi-Feng Wu ◽

Chih-Tsun Huang ◽

Kuo-Liang Cheng ◽

Chih-Wea Wang ◽

Cheng-Wen Wu

Keyword(s):

Simulation Based ◽

Test Algorithm ◽

Algorithm Generation

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Simulation-based test algorithm generation and port scheduling for multi-port memories

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1109/dac.2001.935524 ◽

2002 ◽

Author(s):

Chi-Feng Wu ◽

Chih-Tsun Huang ◽

Kuo-Liang Cheng ◽

Chih-Wea Wang ◽

Cheng-Wen Wu

Keyword(s):

Simulation Based ◽

Test Algorithm ◽

Algorithm Generation

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Fault modeling and test algorithm development for static random access memories

International Test Conference 1988 Proceeding@m_New Frontiers in Testing ◽

10.1109/test.1988.207820 ◽

2003 ◽

Cited By ~ 122

Author(s):

R. Dekker ◽

F. Beenker ◽

L. Thijssen

Keyword(s):

Random Access ◽

Fault Modeling ◽

Algorithm Development ◽

Static Random Access Memories ◽

Test Algorithm

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A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2012.2184107 ◽

2012 ◽

Vol 31 (6) ◽

pp. 941-949 ◽

Cited By ~ 11

Author(s):

Gurgen Harutyunyan ◽

Samvel Shoukourian ◽

Valery Vardanian ◽

Yervant Zorian

Keyword(s):

Fault Detection ◽

New Method ◽

March Test ◽

Test Algorithm ◽

Algorithm Generation

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SRAM delay fault modeling and test algorithm development

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337548 ◽

2004 ◽

Author(s):

Rei-Fu Huang ◽

Yan-Ting Lai ◽

Yung-Fa Chou ◽

Cheng-Wen Wu

Keyword(s):

Fault Modeling ◽

Delay Fault ◽

Algorithm Development ◽

Test Algorithm

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Fault simulation and test algorithm generation for random access memories

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.992771 ◽

2002 ◽

Vol 21 (4) ◽

pp. 480-490 ◽

Cited By ~ 27

Author(s):

Chi-Feng Wu ◽

Chih-Tsun Huang ◽

Kuo-Liang Cheng ◽

Cheng-Wen Wu

Keyword(s):

Fault Simulation ◽

Random Access ◽

Test Algorithm ◽

Algorithm Generation

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Simulation-based test algorithm generation for random access memories

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843857 ◽

2002 ◽

Cited By ~ 19

Author(s):

Chi-Feng Wu ◽

Chih-Tsun Huang ◽

Kuo-Liang Cheng ◽

Cheng-Wen Wu

Keyword(s):

Random Access ◽

Simulation Based ◽

Test Algorithm ◽

Algorithm Generation

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Fault modeling and test algorithm creation strategy for FinFET-based memories

2014 IEEE 32nd VLSI Test Symposium (VTS) ◽

10.1109/vts.2014.6818747 ◽

2014 ◽

Cited By ~ 21

Author(s):

G. Harutyunyan ◽

G. Tshagharyan ◽

V. Vardanian ◽

Y. Zorian

Keyword(s):

Fault Modeling ◽

Test Algorithm

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Genetic-Test Algorithm Is Validated for CAD Assessment

Family Practice News ◽

10.1016/s0300-7073(10)70017-7 ◽

2010 ◽

Vol 40 (1) ◽

pp. 12

Author(s):

MITCHEL L. ZOLER

Keyword(s):

Genetic Test ◽

Test Algorithm

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Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0252 ◽

2007 ◽

Author(s):

Martin Versen ◽

Dorina Diaconescu ◽

Jerome Touzel

Keyword(s):

Failure Mode ◽

Failure Modes ◽

Fault Modeling ◽

Mode Analysis ◽

Root Cause ◽

Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

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