ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)
Latest Publications

TOTAL DOCUMENTS

218

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780381750

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Timing measurement unit with multi-stage TVC for embedded memories

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337651 ◽

2005 ◽

Cited By ~ 1

Author(s):

Kae-Jiun Mo ◽

Shao-Sheng Yang ◽

Tsin-Yuan Chang

Keyword(s):

Measurement Unit ◽

Multi Stage ◽

Timing Measurement ◽

Embedded Memories

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A compressed frame buffer to reduce display power consumption in mobile systems

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337707 ◽

2005 ◽

Cited By ~ 6

Author(s):

Hojun Shim ◽

Nachyuck Chang ◽

M. Pedram

Keyword(s):

Power Consumption ◽

Mobile Systems ◽

Frame Buffer

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Keynote address II - System level design technology for realizing an ambient intelligent environment

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337520 ◽

2005 ◽

Author(s):

R. Lauwereins

Keyword(s):

System Level ◽

Keynote Address ◽

System Level Design ◽

Intelligent Environment ◽

Design Technology ◽

Ambient Intelligent ◽

Level Design

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A. static and dynamic energy reduction technique for I-cache and BTB in embedded processors

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337709 ◽

2005 ◽

Cited By ~ 3

Author(s):

H. Sato ◽

T. Sato

Keyword(s):

Reduction Technique ◽

Energy Reduction ◽

Embedded Processors

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Design-manufacturing interface for 0.13 um and below

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337698 ◽

2005 ◽

Author(s):

A.J. Strojwas

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A small-area high-performance 512-point 2-dimensional FFT single-chip processor

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337637 ◽

2005 ◽

Author(s):

N. Miyarnoto ◽

L. Kaman ◽

K. Maruo ◽

K. Kotani ◽

T. Ohmi

Keyword(s):

Small Area ◽

High Performance ◽

Single Chip

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Enabling on-chip diversity through architectural communication design

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337704 ◽

2005 ◽

Cited By ~ 4

Author(s):

T. Dumitras ◽

S. Kerner ◽

R. Marculescu

Keyword(s):

Communication Design ◽

On Chip

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Compact 12-port multi-bank register file test-chip in 0.35μm CMOS for highly parallel processors

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337644 ◽

2005 ◽

Author(s):

T. Sueyoshi ◽

H. Uchida ◽

H.J. Mattausch ◽

T. Koide ◽

Y. Mitani ◽

...

Keyword(s):

Parallel Processors ◽

Test Chip

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"Signal integrity analysis in the open architecture"

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337596 ◽

2005 ◽

Author(s):

D.M. Petrich

Keyword(s):

Signal Integrity ◽

Open Architecture ◽

Integrity Analysis

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Parametric reduced order modeling for interconnect analysis

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337699 ◽

2005 ◽

Cited By ~ 4

Author(s):

G. Shi ◽

C.-J.R. Shi

Keyword(s):

Reduced Order Modeling ◽

Reduced Order

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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Timing measurement unit with multi-stage TVC for embedded memories

A compressed frame buffer to reduce display power consumption in mobile systems

Keynote address II - System level design technology for realizing an ambient intelligent environment

A. static and dynamic energy reduction technique for I-cache and BTB in embedded processors

Design-manufacturing interface for 0.13 um and below

A small-area high-performance 512-point 2-dimensional FFT single-chip processor

Enabling on-chip diversity through architectural communication design

Compact 12-port multi-bank register file test-chip in 0.35μm CMOS for highly parallel processors

"Signal integrity analysis in the open architecture"

Parametric reduced order modeling for interconnect analysis

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)
Latest Publications