Simulation-based test algorithm generation for random access memories

2002 ◽  
Author(s):  
Chi-Feng Wu ◽  
Chih-Tsun Huang ◽  
Kuo-Liang Cheng ◽  
Cheng-Wen Wu
Keyword(s):  
Random Access ◽  
Simulation Based ◽  
Test Algorithm ◽  
Algorithm Generation

Fault simulation and test algorithm generation for random access memories

2002 ◽  
Vol 21 (4) ◽  
pp. 480-490 ◽  
Author(s):  
Chi-Feng Wu ◽  
Chih-Tsun Huang ◽  
Kuo-Liang Cheng ◽  
Cheng-Wen Wu
Keyword(s):  
Fault Simulation ◽  
Random Access ◽  
Test Algorithm ◽  
Algorithm Generation

Reliable analog resistive switching behaviors achieved using memristive devices in AlOx/HfOx bilayer structure for neuromorphic systems

2021 ◽  
Author(s):  
Meng Qi ◽  
Tianquan Fu ◽  
Huadong Yang ◽  
ye tao ◽  
Chunran Li ◽  
...  
Keyword(s):  
Resistive Switching ◽  
Learning Experience ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Spike Timing ◽  
Information Storage ◽  
Bilayer Structure ◽  
Neuromorphic Computing ◽  
Von Neumann ◽  
Simulation Based

Abstract Human brain synaptic memory simulation based on resistive random access memory (RRAM) has an enormous potential to replace traditional Von Neumann digital computer thanks to several advantages, including its simple structure, high-density integration, and the capability to information storage and neuromorphic computing. Herein, the reliable resistive switching (RS) behaviors of RRAM are demonstrated by engineering AlOx/HfOx bilayer structure. This allows for uniform multibit information storage. Further, the analog switching behaviors are capable of imitate several synaptic learning functions, including learning experience behaviors, short-term plasticity-long-term plasticity transition, and spike-timing-dependent-plasticity (STDP). In addition, the memristor based on STDP learning rules are implemented in image pattern recognition. These results may offer a promising potential of HfOx-based memristors for future information storage and neuromorphic computing applications.

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

2018 ◽  
Author(s):  
S. M. Nair ◽  
R. Bishnoi ◽  
M. B. Tahoori ◽  
G. Tshagharyan ◽  
H. Grigoryan ◽  
...  
Keyword(s):  
Fault Modeling ◽  
Defect Injection ◽  
Test Algorithm ◽  
Algorithm Generation

scholarly journals STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

VLSI Design ◽  
1994 ◽  
Vol 1 (4) ◽  
pp. 327-334
Author(s):  
Rochit Rajsuman ◽  
Kamal Rajkanan
Keyword(s):  
Fault Diagnosis ◽  
Design Method ◽  
Random Access ◽  
Standard Test ◽  
Test Time ◽  
Design Time ◽  
Memory Address ◽  
Hardware Overhead ◽  
Test Algorithm ◽  
Time Required

We present a design method (called STD architecture) to design large memories so that the test time does not increase with the increasing size of memory. Large memories can be constructed by using several small blocks of memory. The memory address decoder is divided into two or more levels and designed such that during the test mode all small memory blocks are accessed together. With the help of modified decoder, all small memory blocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory is equal to the time required to test one small block. The proposed design is highly structured and hardware overhead is negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method a constant test time can be achieved irrespective of the memory size. STD architecture is applicable to memory chips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis.

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