Multiple tests for each gate delay fault: higher coverage and lower test application cost

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584089 ◽

2006 ◽

Cited By ~ 10

Author(s):

S. Irajpour ◽

S.K. Gupta ◽

M.A. Breuer

Keyword(s):

Gate Delay ◽

Delay Fault ◽

Multiple Tests ◽

Test Application ◽

Lower Test ◽

Gate Delay Fault

Download Full-text

Gate-delay-fault testability properties of multiplexor-based networks

Formal Methods in System Design ◽

10.1007/bf01383945 ◽

1993 ◽

Vol 2 (1) ◽

pp. 93-112 ◽

Cited By ~ 1

Author(s):

Pranav Ashar ◽

Srinivas Devadas ◽

Kurt Keutzer

Keyword(s):

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Test generation for multiple-threshold gate-delay fault model

Proceedings 10th Asian Test Symposium ◽

10.1109/ats.2001.990290 ◽

2002 ◽

Cited By ~ 7

Author(s):

M. Nakao ◽

Y. Kiyoshige ◽

K. Hatayama ◽

Y. Sato ◽

T. Nagumo

Keyword(s):

Test Generation ◽

Fault Model ◽

Gate Delay ◽

Delay Fault ◽

Multiple Threshold ◽

Gate Delay Fault ◽

Threshold Gate

Download Full-text

On the fault coverage of gate delay fault detecting tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.559333 ◽

1997 ◽

Vol 16 (1) ◽

pp. 78-94 ◽

Cited By ~ 27

Author(s):

A.K. Pramanick ◽

S.M. Reddy

Keyword(s):

Fault Coverage ◽

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

DFSIM: a gate-delay fault simulator for sequential circuits

Proceedings ED&TC European Design and Test Conference ◽

10.1109/edtc.1996.494160 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Cavallera ◽

P. Girard ◽

C. Landrault ◽

S. Pravossoudovitch

Keyword(s):

Sequential Circuits ◽

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Gate-delay fault test with conventional scan-design

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326825 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Kunzmann ◽

F. Bohland

Keyword(s):

Gate Delay ◽

Scan Design ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Gate delay fault test generation for non-scan circuits

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470379 ◽

2002 ◽

Cited By ~ 2

Author(s):

G. van Brakel ◽

U. Glaser ◽

H.G. Kerkhoff ◽

H.T. Vierhaus

Keyword(s):

Test Generation ◽

Gate Delay ◽

Delay Fault ◽

Scan Circuits ◽

Gate Delay Fault

Download Full-text

Gate-delay fault diagnosis using the inject-and-evaluate paradigm

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. ◽

10.1109/dftvs.2002.1173508 ◽

2003 ◽

Cited By ~ 2

Author(s):

Horng-Bin Wang ◽

Shi-Yu Huang ◽

Jing-Reng Huang

Keyword(s):

Fault Diagnosis ◽

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks

1991, Proceedings. International Test Conference ◽

10.1109/test.1991.519755 ◽

2005 ◽

Cited By ~ 10

Author(s):

P. Ashar ◽

S. Devadas ◽

K. Keutzer

Keyword(s):

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Identification of single gate delay fault redundancies

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276213 ◽

2003 ◽

Author(s):

D. Brand ◽

V.S. Iyengar

Keyword(s):

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

Download Full-text

Delay Faults Testing

Design and Test Technology for Dependable Systems-on-Chip - Advances in Computer and Electrical Engineering ◽

10.4018/978-1-60960-212-3.ch017 ◽

2011 ◽

pp. 377-394 ◽

Cited By ~ 1

Author(s):

Marcel Baláž ◽

Roland Dobai ◽

Elena Gramatová

Keyword(s):

New Technologies ◽

Asynchronous Circuits ◽

Clock Frequency ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Test Application ◽

Application Techniques ◽

Quality And Reliability

Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.

Download Full-text