SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level

Register-transfer level deductive fault simulation using decision diagrams

2010 12th Biennial Baltic Electronics Conference ◽

10.1109/bec.2010.5631842 ◽

2010 ◽

Cited By ~ 2

Author(s):

Uljana Reinsalu ◽

Jaan Raik ◽

Raimund Ubar

Keyword(s):

Fault Simulation ◽

Register Transfer Level ◽

Decision Diagrams ◽

Register Transfer

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A data path verifier for register transfer level using temporal logic language Tokio

Lecture Notes in Computer Science - Computer-Aided Verification ◽

10.1007/bfb0023721 ◽

2005 ◽

pp. 76-85 ◽

Cited By ~ 2

Author(s):

Hiroshi Nakamura ◽

Yuji Kukimoto ◽

Masahiro Fujita ◽

Hidehiko Tanaka

Keyword(s):

Temporal Logic ◽

Register Transfer Level ◽

Data Path ◽

Register Transfer

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A design-for-testability technique for register-transfer level circuits using control/data flow extraction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.712102 ◽

1998 ◽

Vol 17 (8) ◽

pp. 706-723 ◽

Cited By ~ 34

Author(s):

I. Ghosh ◽

A. Raghunathan ◽

N.K. Jha

Keyword(s):

Data Flow ◽

Design For Testability ◽

Register Transfer Level ◽

Control Data ◽

Register Transfer

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Automatic data path extraction in large-scale register-transfer level designs

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865144 ◽

2014 ◽

Author(s):

Wei Song ◽

Jim Garside ◽

Doug Edwards

Keyword(s):

Large Scale ◽

Register Transfer Level ◽

Data Path ◽

Automatic Data ◽

Register Transfer ◽

Path Extraction

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Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2002.800450 ◽

2002 ◽

Vol 21 (8) ◽

pp. 877-888 ◽

Cited By ~ 3

Author(s):

R. Karri ◽

B. Iyer ◽

I. Koren

Keyword(s):

Register Transfer Level ◽

Data Path ◽

Register Transfer ◽

Path Synthesis

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Practical design assistance at register transfer level using a data path verifier

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1990.130171 ◽

2002 ◽

Cited By ~ 1

Author(s):

H. Nakamura ◽

Y. Kukimoto ◽

M. Fujita ◽

H. Tanaka

Keyword(s):

Register Transfer Level ◽

Data Path ◽

Practical Design ◽

Register Transfer

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A data path verifier for register transfer level using temporal logic language Tokio

Computer-Aided Verification ’90 - DIMACS Series in Discrete Mathematics and Theoretical Computer Science ◽

10.1090/dimacs/003/30 ◽

1991 ◽

pp. 493-504

Author(s):

H. Nakamura ◽

Y. Kukimoto ◽

M. Fujita ◽

H. Tanaka

Keyword(s):

Temporal Logic ◽

Register Transfer Level ◽

Data Path ◽

Register Transfer

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VFSim: Concurrent Fault Simulation at Register Transfer Level

Journal of Computer Science and Technology ◽

10.1007/s11390-005-0175-1 ◽

2005 ◽

Vol 20 (2) ◽

pp. 175-186 ◽

Cited By ~ 1

Author(s):

Li Shen

Keyword(s):

Fault Simulation ◽

Register Transfer Level ◽

Register Transfer ◽

Concurrent Fault Simulation

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Cloud computing and distributed platforms ? Data flow, data categories and data use

10.3403/30404144 ◽

2020 ◽

Keyword(s):

Cloud Computing ◽

Data Flow ◽

Data Use ◽

Flow Data

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