Practical design assistance at register transfer level using a data path verifier

A data path verifier for register transfer level using temporal logic language Tokio

Lecture Notes in Computer Science - Computer-Aided Verification ◽

10.1007/bfb0023721 ◽

2005 ◽

pp. 76-85 ◽

Cited By ~ 2

Author(s):

Hiroshi Nakamura ◽

Yuji Kukimoto ◽

Masahiro Fujita ◽

Hidehiko Tanaka

Keyword(s):

Temporal Logic ◽

Register Transfer Level ◽

Data Path ◽

Register Transfer

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Automatic data path extraction in large-scale register-transfer level designs

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865144 ◽

2014 ◽

Author(s):

Wei Song ◽

Jim Garside ◽

Doug Edwards

Keyword(s):

Large Scale ◽

Register Transfer Level ◽

Data Path ◽

Automatic Data ◽

Register Transfer ◽

Path Extraction

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Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2002.800450 ◽

2002 ◽

Vol 21 (8) ◽

pp. 877-888 ◽

Cited By ~ 3

Author(s):

R. Karri ◽

B. Iyer ◽

I. Koren

Keyword(s):

Register Transfer Level ◽

Data Path ◽

Register Transfer ◽

Path Synthesis

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A data path verifier for register transfer level using temporal logic language Tokio

Computer-Aided Verification ’90 - DIMACS Series in Discrete Mathematics and Theoretical Computer Science ◽

10.1090/dimacs/003/30 ◽

1991 ◽

pp. 493-504

Author(s):

H. Nakamura ◽

Y. Kukimoto ◽

M. Fujita ◽

H. Tanaka

Keyword(s):

Temporal Logic ◽

Register Transfer Level ◽

Data Path ◽

Register Transfer

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SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805785 ◽

2003 ◽

Cited By ~ 1

Author(s):

S. Yadavalli ◽

S.M. Reddy

Keyword(s):

Data Flow ◽

Fault Simulation ◽

Register Transfer Level ◽

Data Path ◽

Flow Data ◽

Register Transfer

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2406 ◽

2011 ◽

Vol 2 (4) ◽

pp. 61-68

Author(s):

M S Suma

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Sequential Circuits ◽

Register Transfer ◽

Combinational And Sequential Circuits

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Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Cited By ~ 12

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Dft Method ◽

Register Transfer Level ◽

Register Transfer

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Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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