Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOSFET) Including High-Voltage and Floating-Body Effects

2011 ◽  
Vol 58 (10) ◽  
pp. 3485-3493 ◽  
Author(s):  
Tarun Kumar Agarwal ◽  
Amit Ranjan Trivedi ◽  
Vaidyanathan Subramanian ◽  
M. Jagadesh Kumar
2020 ◽  
Vol 217 (9) ◽  
pp. 1900948 ◽  
Author(s):  
Hyungjin Park ◽  
Jean-Pierre Colinge ◽  
Sorin Cristoloveanu ◽  
Maryline Bawedin

1988 ◽  
Vol 24 (4) ◽  
pp. 238 ◽  
Author(s):  
S.S. Tsao ◽  
D.R. Myers ◽  
G.K. Celler

2011 ◽  
Vol 20 (03) ◽  
pp. 471-484 ◽  
Author(s):  
LIANG ZUO ◽  
ROBERT GREENWELL ◽  
SYED K. ISLAM ◽  
M. A. HUQUE ◽  
BENJAMIN J. BLALOCK ◽  
...  

In recent years, increasing demand for hybrid electric vehicles (HEVs) has generated the need for reliable and low-cost high-temperature electronics which can operate at the high temperatures under the hood of these vehicles. A high-voltage and high temperature gate-driver integrated circuit for SiC FET switches with short circuit protection has been designed and implemented in a 0.8-micron silicon-on-insulator (SOI) high-voltage process. The prototype chip has been successfully tested up to 200°C ambient temperature without any heat sink or cooling mechanism. This gate-driver chip can drive SiC power FETs of the DC-DC converters in a HEV, and future chip modifications will allow it to drive the SiC power FETs of the traction drive inverter. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175ΰC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module.


MRS Advances ◽  
2018 ◽  
Vol 3 (57-58) ◽  
pp. 3347-3357
Author(s):  
S. Dutta ◽  
T. Chavan ◽  
S. Shukla ◽  
V. Kumar ◽  
A. Shukla ◽  
...  

Abstract:Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.


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