Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices
2004 ◽
Vol 51
(5)
◽
pp. 708-713
◽
2004 ◽
Vol 25
(5)
◽
pp. 331-333
◽
Keyword(s):
2000 ◽
Vol 44
(10)
◽
pp. 1819-1824
◽
2020 ◽
Vol 23
(3)
◽
pp. 227-252
Keyword(s):
2005 ◽
Vol 52
(7)
◽
pp. 1649-1655
◽