scholarly journals An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

2006 ◽  
Author(s):  
Keith Boyle ◽  
Sai Mohan Kilambi ◽  
Rafal Dlugosz ◽  
Kris Iniewski ◽  
Vincent Gaudet
Keyword(s):  
Power Consumption ◽  
Analog To Digital Converters ◽  
Feature Size ◽  
Effective Power ◽  
Analog To Digital ◽  
Size Scaling

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

scholarly journals A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization

2016 ◽  
Vol 16 (1) ◽  
pp. 28-34 ◽  
Author(s):  
Jelena Jovanović ◽  
Dragan Denić
Keyword(s):  
Power Consumption ◽  
Piecewise Linear ◽  
Circuit Complexity ◽  
Cost Effective ◽  
Analog To Digital Converters ◽  
Digital Converter ◽  
Analog To Digital ◽  
Cost Effective Method ◽  
Conversion Stage ◽  
Sensor Linearization

Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS

2009 ◽  
Vol 18 (05) ◽  
pp. 933-945
Author(s):  
CHIA-CHUN TSAI ◽  
KAI-WEI HONG ◽  
TRONG-YEN LEE
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Clock Cycle ◽  
Sampling Rate ◽  
Reducing Power ◽  
Power Reduction ◽  
Analog To Digital Converters ◽  
Bisection Method ◽  
Flash Adc ◽  
Analog To Digital

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

scholarly journals 1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019 ◽  
Vol 8 (6S4) ◽  
pp. 1322-1326
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Slew Rate ◽  
Two Stage ◽  
Analog To Digital ◽  
Low Offset ◽  
Medical Equipments

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

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