Approaches for reducing power consumption of the high-resolution pipelined analog-to-digital converters

2018 ◽  
Author(s):  
Aleksandr V. Sidun ◽  
Ivan M. Piatak
Keyword(s):  
High Resolution ◽  
Power Consumption ◽  
Reducing Power ◽  
Analog To Digital Converters ◽  
Analog To Digital

A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS

2009 ◽  
Vol 18 (05) ◽  
pp. 933-945
Author(s):  
CHIA-CHUN TSAI ◽  
KAI-WEI HONG ◽  
TRONG-YEN LEE
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Clock Cycle ◽  
Sampling Rate ◽  
Reducing Power ◽  
Power Reduction ◽  
Analog To Digital Converters ◽  
Bisection Method ◽  
Flash Adc ◽  
Analog To Digital

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

scholarly journals A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1968
Author(s):  
Juyong Lee ◽  
Seungjun Lee ◽  
Kihyun Kim ◽  
Hyungil Chae
Keyword(s):  
High Resolution ◽  
Power Consumption ◽  
Power Efficiency ◽  
Sampling Rate ◽  
High Gain ◽  
Sar Adc ◽  
Measured Signal ◽  
Noise Shaping ◽  
Analog To Digital ◽  
Digital Correction

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The (= SNDR + BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

scholarly journals Analog to Digital Converters (ADC): A Literature Review

2020 ◽  
Vol 184 ◽  
pp. 01025
Author(s):  
Hemlata Dalmia ◽  
Sanjeet K. Sinha
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Communication Technology ◽  
High Performance ◽  
Reducing Power ◽  
Digital Signal ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Cmos Scaling ◽  
Analog To Digital Conversion

The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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