scholarly journals Low Power Consumption Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters for 33-Megapixel 120-fps CMOS Image Sensor

2013 ◽  
Vol 67 (8) ◽  
pp. J286-J295
Author(s):  
Toshihisa Watabe ◽  
Kazuya Kitamura ◽  
Takehide Sawamoto ◽  
Tomohiko Kosugi ◽  
Tomoyuki Akahori ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Analog To Digital Converters ◽  
Low Power Consumption ◽  
Two Stage ◽  
Analog To Digital ◽  
Cyclic Analog

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

2012 ◽  
Vol 59 (12) ◽  
pp. 3426-3433 ◽  
Author(s):  
Kazuya Kitamura ◽  
Toshihisa Watabe ◽  
Takehide Sawamoto ◽  
Tomohiko Kosugi ◽  
Tomoyuki Akahori ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Analog To Digital Converters ◽  
Two Stage ◽  
Analog To Digital ◽  
Cyclic Analog

scholarly journals 1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019 ◽  
Vol 8 (6S4) ◽  
pp. 1322-1326
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Slew Rate ◽  
Two Stage ◽  
Analog To Digital ◽  
Low Offset ◽  
Medical Equipments

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

Compact Low-Power Analog-to-Digital Converters using Multi-State Spatial Wavefunction-Switched (SWS) FETs

2014 ◽  
Vol 23 (01n02) ◽  
pp. 1450005
Author(s):  
Murali Lingalugari ◽  
John Chandy ◽  
Faquir Jain ◽  
El-Sayed Hasaneen ◽  
Evan Heller
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Analog To Digital Converters ◽  
Data Conversion ◽  
Low Power Consumption ◽  
Quantum Mechanical ◽  
Multiple Quantum ◽  
Analog To Digital ◽  
Electron Wavefunction

In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

Using Dual-Channel D/A Converters Design Successive Approximation A/D Converter

2015 ◽  
Vol 719-720 ◽  
pp. 611-614
Author(s):  
Jia Rong Wang ◽  
Xiao Dong Xia ◽  
Zong Da Zhang ◽  
Han Yang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Low Cost ◽  
Electronic Devices ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Digital Converter ◽  
Analog To Digital ◽  
Dual Channel

The successive approximation analog-to-digital converter (ADC) has been widely used in electronic devices due to the corresponding characteristics which are low cost, low power consumption, high accuracy and so on. This paper expounds a design of successive approximation A / D converter to show how to use TCL5615 which is a dual-channel serial 10-bit D/A converter (DAC) to make the conversion accuracy to reach 14-bit.

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